main/postmarketos-base-ui: fix netboot mode

Do not allow NetworkManager managing the USB interface in netboot mode.
Netboot mode requires a fixed connection without NetworkManager possible
interrupting it when taking over management from initfs.
This fixes boot issues for the netboot use case.

.ci/build-armhf.sh

@@ -0,0 +1 @@
+lib/build_changed_aports.sh

.ci/build-riscv64.sh

@@ -0,0 +1 @@
+lib/build_changed_aports.sh

.ci/build-x86.sh

@@ -0,0 +1 @@
+lib/build_changed_aports.sh

.ci/shellcheck.sh

@@ -17,12 +17,12 @@ sh_files="
 	./main/mdss-fb-init-hack/mdss-fb-init-hack.sh
 	./main/osk-sdl/unlock.sh
 	./main/postmarketos-base/rootfs-usr-lib-firmwareload.sh
+	./main/postmarketos-base-ui/rootfs-usr-lib-NetworkManager-dispatcher.d-50-dns-filter.sh
 	./main/postmarketos-base-ui/rootfs-usr-lib-NetworkManager-dispatcher.d-50-tethering.sh
 	./main/postmarketos-installkernel/installkernel-pmos
 	./main/postmarketos-initramfs/init.sh
 	./main/postmarketos-initramfs/init_functions.sh
 	./main/postmarketos-mkinitfs-hook-debug-shell/20-debug-shell.sh
-	./main/postmarketos-mkinitfs-hook-debug-shell/setup_usb_storage.sh
 	./main/postmarketos-mkinitfs-hook-netboot/netboot.sh
 	./main/postmarketos-update-kernel/update-kernel.sh
 	./main/ttyescape/*.post-install

.ci/testcases/add_pmbootstrap_to_import_path/__init__.py

@@ -7,7 +7,7 @@ import sys
 import os
 import importlib
 import importlib.util
-from site import getsitepackages
+from distutils.sysconfig import get_python_lib
 
 
 def path_pmbootstrap():
@@ -24,14 +24,13 @@ def path_pmbootstrap():
         sys.exit(1)
 
     # Resolve the symlink and verify the folder
-    directory = os.path.dirname(os.path.realpath(bin))
-    if os.path.exists(directory + "/pmb/__init__.py"):
-        return directory
+    dir = os.path.dirname(os.path.realpath(bin))
+    if os.path.exists(dir + "/pmb/__init__.py"):
+        return dir
 
-    directories = getsitepackages()
-    for directory in directories:
-        if os.path.exists(directory + "/pmb/__init__.py"):
-            return directory
+    dir = get_python_lib()
+    if os.path.exists(dir + "/pmb/__init__.py"):
+        return dir
 
     # Symlink not set up properly
     print("ERROR: 'pmbootstrap' is not a symlink to pmbootstrap.py")

.ci/testcases/test_directory_structure.py

@@ -30,7 +30,7 @@ def test_directories():
 # Ensure no file in pmaports are executable.
 # see https://gitlab.com/postmarketOS/pmaports/-/issues/593.
 def test_executable_files():
-    for file in glob.iglob("[!temp]**/**/*", recursive=True):
+    for file in glob.iglob("**/*", recursive=True):
         if os.path.isdir(file) or os.path.islink(file):
             continue
             # still check other less common inode types

.ecrc

@@ -1,4 +1,3 @@
 {
-  "SpacesAftertabs": true,
-  "Exclude": ["temp"]
+  "SpacesAftertabs": true
 }

.gitlab-ci.yml

@@ -18,7 +18,7 @@ stages:
 # https://docs.gitlab.com/ee/ci/merge_request_pipelines/index.html#excluding-certain-jobs
 .only-default: &only-default
   only:
-    - v23.12
+    - master
     - merge_requests
     - tags
 
@@ -100,7 +100,7 @@ kernel-kconfig:
   stage: lint
   only:
     refs:
-      - v23.12
+      - master
       - merge_requests
     changes:
       - device/*/linux-*/config-*
@@ -140,6 +140,11 @@ build-x86_64:
   script:
     - .ci/build-x86_64.sh
 
+build-x86:
+  extends: .build
+  script:
+    - .ci/build-x86.sh
+
 build-aarch64:
   extends: .build
   script:
@@ -149,3 +154,13 @@ build-armv7:
   extends: .build
   script:
     - .ci/build-armv7.sh
+
+build-armhf:
+  extends: .build
+  script:
+    - .ci/build-armhf.sh
+
+build-riscv64:
+  extends: .build
+  script:
+    - .ci/build-riscv64.sh

channels.cfg

@@ -0,0 +1,51 @@
+# Reference: https://postmarketos.org/channels.cfg
+[channels.cfg]
+recommended=edge
+
+[edge]
+description=Rolling release / Most devices / Occasional breakage: https://postmarketos.org/edge
+branch_pmaports=master
+branch_aports=master
+mirrordir_alpine=edge
+
+[v23.06]
+description=Latest release / Recommended for best stability
+branch_pmaports=v23.06
+branch_aports=3.18-stable
+mirrordir_alpine=v3.18
+
+[v22.12]
+description=Old release (unsupported)
+branch_pmaports=v22.12
+branch_aports=3.17-stable
+mirrordir_alpine=v3.17
+
+[v22.06]
+description=Old release (unsupported)
+branch_pmaports=v22.06
+branch_aports=3.16-stable
+mirrordir_alpine=v3.16
+
+[v21.12]
+description=Old release (unsupported)
+branch_pmaports=v21.12
+branch_aports=3.15-stable
+mirrordir_alpine=v3.15
+
+[v21.06]
+description=Old release (unsupported)
+branch_pmaports=v21.06
+branch_aports=3.14-stable
+mirrordir_alpine=v3.14
+
+[v21.03]
+description=Old release (unsupported)
+branch_pmaports=v21.03
+branch_aports=3.13-stable
+mirrordir_alpine=v3.13
+
+[v20.05]
+description=Old release (unsupported)
+branch_pmaports=v20.05
+branch_aports=3.12-stable
+mirrordir_alpine=v3.12

cross/busybox-static-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-aarch64
 pkgver=1.36.1
-pkgrel=19
+pkgrel=6
 
 _arch="aarch64"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -21,16 +21,16 @@ pkgdesc="Statically linked Busybox for $_arch"
 _target="$(arch_to_hostspec $_arch)"
 
 source="
-	busybox-static-$pkgver-r$pkgrel-$_arch-v3.19.apk::$_mirror/v3.19/main/$_arch/busybox-static-$pkgver-r$pkgrel.apk
+	busybox-static-$pkgver-r$pkgrel-$_arch-edge.apk::$_mirror/edge/main/$_arch/busybox-static-$pkgver-r$pkgrel.apk
 "
 
 package() {
 	mkdir -p "$pkgdir/usr/$_target"
 	cd "$pkgdir/usr/$_target"
-	tar -xf $srcdir/busybox-static-$pkgver-r$pkgrel-$_arch-v3.19.apk
+	tar -xf $srcdir/busybox-static-$pkgver-r$pkgrel-$_arch-edge.apk
 	rm .PKGINFO .SIGN.*
 }
 
 sha512sums="
-aa58bb098d78beddc923a58599688b68768b311759d4acf05d75ba26c5969a31b9faed1b65b600688a5670d2d0c97562f2ebad529864a16eb987b9f4b3ec2924  busybox-static-1.36.1-r19-aarch64-v3.19.apk
+2645e724a4762ae18eaf1eee7048a30d86a6745dd7d4dc296080f40ce0ceb334b89a7dbad05f56657ea3794361e14d03b0f7f03ae83ad3d34f28ec025e45bbee  busybox-static-1.36.1-r6-aarch64-edge.apk
 "

cross/busybox-static-armhf/APKBUILD

@@ -0,0 +1,36 @@
+# Automatically generated aport, do not edit!
+# Generator: pmbootstrap aportgen busybox-static-armhf
+
+# Stub for apkbuild-lint
+if [ -z "$(type -t arch_to_hostspec)" ]; then
+	arch_to_hostspec() { :; }
+fi
+
+pkgname=busybox-static-armhf
+pkgver=1.36.1
+pkgrel=6
+
+_arch="armhf"
+_mirror="http://dl-4.alpinelinux.org/alpine/"
+
+url="http://busybox.net"
+license="GPL2"
+arch="x86_64"
+options="!check !strip"
+pkgdesc="Statically linked Busybox for $_arch"
+_target="$(arch_to_hostspec $_arch)"
+
+source="
+	busybox-static-$pkgver-r$pkgrel-$_arch-edge.apk::$_mirror/edge/main/$_arch/busybox-static-$pkgver-r$pkgrel.apk
+"
+
+package() {
+	mkdir -p "$pkgdir/usr/$_target"
+	cd "$pkgdir/usr/$_target"
+	tar -xf $srcdir/busybox-static-$pkgver-r$pkgrel-$_arch-edge.apk
+	rm .PKGINFO .SIGN.*
+}
+
+sha512sums="
+6ac00686670a1e5fed1221b9e2e88ecc9e46af83ae1f63b844155ce7d122cb247169fa2c35a20154618c536f514ba53f74d4385e92ae2b4c930df7938822d4b8  busybox-static-1.36.1-r6-armhf-edge.apk
+"

cross/busybox-static-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armv7
 pkgver=1.36.1
-pkgrel=19
+pkgrel=6
 
 _arch="armv7"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -21,16 +21,16 @@ pkgdesc="Statically linked Busybox for $_arch"
 _target="$(arch_to_hostspec $_arch)"
 
 source="
-	busybox-static-$pkgver-r$pkgrel-$_arch-v3.19.apk::$_mirror/v3.19/main/$_arch/busybox-static-$pkgver-r$pkgrel.apk
+	busybox-static-$pkgver-r$pkgrel-$_arch-edge.apk::$_mirror/edge/main/$_arch/busybox-static-$pkgver-r$pkgrel.apk
 "
 
 package() {
 	mkdir -p "$pkgdir/usr/$_target"
 	cd "$pkgdir/usr/$_target"
-	tar -xf $srcdir/busybox-static-$pkgver-r$pkgrel-$_arch-v3.19.apk
+	tar -xf $srcdir/busybox-static-$pkgver-r$pkgrel-$_arch-edge.apk
 	rm .PKGINFO .SIGN.*
 }
 
 sha512sums="
-570dd6f150d74bafec0b4485ced760e815a1550372251cba8b51e1e4193ead71b81c2262a04a6f279fad1ebacc7c792eb825614d2f67f57c4f3b0b33d11033ab  busybox-static-1.36.1-r19-armv7-v3.19.apk
+e59173164044ecabfe9e6784d90143e62b7346c0db4e36fbb4df7e4f6916b1d5823284ff98a9408a1af4f8406f6f9c5f60908e1b748e4510a21cc60a1eac4448  busybox-static-1.36.1-r6-armv7-edge.apk
 "

cross/crossdirect/APKBUILD

@@ -1,6 +1,3 @@
-# Maintainer: Oliver Smith <ollieparanoid@postmarketos.org>
-# https://wiki.postmarketos.org/wiki/Pmbootstrap:_Cross_Compiling
-#
 # Wrapper for the "crossdirect" compilation method.
 # pmbootstrap mounts the native chroot in the foreign arch (e.g. armhf) chroot
 # as /native. This package gets installed into the native chroot, and creates
@@ -19,7 +16,7 @@
 # version is implemented as simple shell wrappers.
 
 pkgname=crossdirect
-pkgver=5.1.0
+pkgver=5
 pkgrel=0
 pkgdesc="Wrappers to launch native cross compilers in foreign chroots"
 url="https://postmarketOS.org"
@@ -79,10 +76,9 @@ package() {
 		ln -s ../rustc.sh rustc
 	done
 }
-
 sha512sums="
 0f4b48f250425dc57f63955fc8b38477d23db793bee367c3fbe03c3d2a559ba576434d07518310db4cae9d90d501af4051b80038b10fae94b980e537fc9374ad  cargo.sh
 500107e5aff8b34e74b54982ebcd447fc41bc8283956d506561b031a055cb30ec12698047c2604918b4b6d8560fe03db427a63dff2b83c907e8494b7f5233f29  crossdirect.c
-de2aa6929bbff5db9132673e667f4525b333d062cb1f7a0597dd924de9e5c7215a9f8e2e6263b6fb5ace06f2c4b64f4ebfd0ede9b78add07c2cd08ec8613e98f  rustc.sh
+2c41410a9ef2dab31403545e55e2464f2ee4e7056ffbcd3bc5810d582311801496b88d55307f17ce6acf766e9c867d30d05f2b0d8d46bf77a5e8f0495d6bc24e  rustc.sh
 ea9bf8db3810d03d0a7395057f3d6e57f7127d87c55deaedc171c255288f5f3cc6fbcc680a5a1b92786cf573875d5dc22521173799fe2639acc97d0715ff905b  rust-qemu-linker.sh
 "

cross/crossdirect/rustc.sh

@@ -5,15 +5,8 @@ if [ -n "$CROSSDIRECT_DEBUG" ]; then
 fi
 
 # return the correct host architecture when cargo requests it
-if [ "$*" = "-vV" ] || [ "$*" = "-V" ]; then
-	exec /usr/bin/rustc "$*"
-fi
-
-# pmbootstrap installs sccache when building a rust program, unless --no-ccache
-# is set. In that case it also sets CCACHE_DISABLE.
-SCCACHE=/native/usr/bin/sccache
-if ! [ -e "$SCCACHE" ] || [ -n "$CCACHE_DISABLE" ]; then
-	SCCACHE=""
+if [ "$*" = "-vV" ]; then
+	exec /usr/bin/rustc -vV
 fi
 
 # We expect the right target to be set in the arguments if compiling for the
@@ -21,17 +14,12 @@ fi
 # automatically. If no target is provided, this is probably a macro or a
 # build script, so it should be compiled for the native architecture.
 if echo "$*" | grep -qFe "--target"; then
-	# Not using sccache when building for foreign architecture, as it
-	# doesn't cache the output with "Non-cacheable reasons: --sysroot"
-	LD_LIBRARY_PATH=/native/lib:/native/usr/lib \
-		/native/usr/bin/rustc \
+	LD_LIBRARY_PATH=/native/lib:/native/usr/lib /native/usr/bin/rustc \
 		-Clinker=/native/usr/lib/crossdirect/rust-qemu-linker \
 		--sysroot=/usr \
 		"$@"
 else
-	PATH=/native/usr/bin:/native/bin \
-	LD_LIBRARY_PATH=/native/lib:/native/usr/lib \
-		$SCCACHE \
+	PATH=/native/usr/bin:/native/bin LD_LIBRARY_PATH=/native/lib:/native/usr/lib \
 		/native/usr/bin/rustc \
 		-Clink-arg=-Wl,-rpath,/native/lib:/native/usr/lib \
 		"$@"

cross/gcc-aarch64/0035-Fix-ICE-observed-in-PR110280.patch

@@ -0,0 +1,61 @@
+From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
+From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+Date: Fri, 23 Jun 2023 15:27:17 +0530
+Subject: [PATCH 35/35] Fix ICE observed in PR110280.
+
+gcc/ChangeLog:
+	PR tree-optimization/110280
+	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
+	using build_vector_from_val with the element of input operand, and
+	mask's type if operand and mask's types don't match.
+
+gcc/testsuite/ChangeLog:
+	PR tree-optimization/110280
+	* gcc.target/aarch64/sve/pr110280.c: New test.
+---
+ gcc/match.pd                                    |  9 ++++++++-
+ gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
+ 2 files changed, 20 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+
+diff --git a/gcc/match.pd b/gcc/match.pd
+index 91182448250..c3bb4fbc0a7 100644
+--- a/gcc/match.pd
++++ b/gcc/match.pd
+@@ -8292,7 +8292,14 @@ and,
+ 
+ (simplify
+  (vec_perm vec_same_elem_p@0 @0 @1)
+- @0)
++ (if (types_match (type, TREE_TYPE (@0)))
++  @0
++  (with
++   {
++     tree elem = uniform_vector_p (@0);
++   }
++   (if (elem)
++    { build_vector_from_val (type, elem); }))))
+ 
+ /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
+ (simplify
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+new file mode 100644
+index 00000000000..d3279f38362
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fdump-tree-optimized" } */
++
++#include "arm_sve.h"
++
++svuint32_t l()
++{
++  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
++  return svld1rq_u32(svptrue_b8(), lanes);
++}
++
++/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
+-- 
+2.41.0
+

cross/gcc-aarch64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-aarch64/APKBUILD

@@ -24,8 +24,8 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-aarch64
-pkgver=13.2.1_git20231014
-# i.e. 13.2.1, must match gcc/BASE-VER
+pkgver=13.1.1_git20230722
+# i.e. 13.1.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-aarch64
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for aarch64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -268,13 +268,9 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+	0035-Fix-ICE-observed-in-PR110280.patch
 	"
 
-# secfixes:
-#   13.2.1_git20231014-r0:
-#     - CVE-2023-4039
-
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -787,7 +783,7 @@ gdb() {
 }
 
 sha512sums="
-406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
+284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -822,5 +818,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
 "

cross/gcc-armhf/0035-Fix-ICE-observed-in-PR110280.patch

@@ -0,0 +1,61 @@
+From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
+From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+Date: Fri, 23 Jun 2023 15:27:17 +0530
+Subject: [PATCH 35/35] Fix ICE observed in PR110280.
+
+gcc/ChangeLog:
+	PR tree-optimization/110280
+	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
+	using build_vector_from_val with the element of input operand, and
+	mask's type if operand and mask's types don't match.
+
+gcc/testsuite/ChangeLog:
+	PR tree-optimization/110280
+	* gcc.target/aarch64/sve/pr110280.c: New test.
+---
+ gcc/match.pd                                    |  9 ++++++++-
+ gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
+ 2 files changed, 20 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+
+diff --git a/gcc/match.pd b/gcc/match.pd
+index 91182448250..c3bb4fbc0a7 100644
+--- a/gcc/match.pd
++++ b/gcc/match.pd
+@@ -8292,7 +8292,14 @@ and,
+ 
+ (simplify
+  (vec_perm vec_same_elem_p@0 @0 @1)
+- @0)
++ (if (types_match (type, TREE_TYPE (@0)))
++  @0
++  (with
++   {
++     tree elem = uniform_vector_p (@0);
++   }
++   (if (elem)
++    { build_vector_from_val (type, elem); }))))
+ 
+ /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
+ (simplify
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+new file mode 100644
+index 00000000000..d3279f38362
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fdump-tree-optimized" } */
++
++#include "arm_sve.h"
++
++svuint32_t l()
++{
++  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
++  return svld1rq_u32(svptrue_b8(), lanes);
++}
++
++/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
+-- 
+2.41.0
+

cross/gcc-armhf/APKBUILD

@@ -1,8 +1,8 @@
 # Automatically generated aport, do not edit!
-# Generator: pmbootstrap aportgen gcc-x86
+# Generator: pmbootstrap aportgen gcc-armhf
 # Based on: main/gcc (from Alpine)
 
-CTARGET_ARCH=x86
+CTARGET_ARCH=armhf
 CTARGET="$(arch_to_hostspec ${CTARGET_ARCH})"
 LANG_D=false
 LANG_OBJC=false
@@ -23,9 +23,9 @@ CBUILDROOT="/"
 
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
-pkgname=gcc-x86
-pkgver=13.2.1_git20231014
-# i.e. 13.2.1, must match gcc/BASE-VER
+pkgname=gcc-armhf
+pkgver=13.1.1_git20230722
+# i.e. 13.1.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -33,17 +33,17 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CBUILD" != "$CHOST" ] && _cross="-$CARCH" || _cross=""
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
-pkgname=gcc-x86
-pkgrel=0
-pkgdesc="Stage2 cross-compiler for x86"
+pkgname=gcc-armhf
+pkgrel=2
+pkgdesc="Stage2 cross-compiler for armhf"
 url="https://gcc.gnu.org"
 arch="x86_64"
 license="GPL-2.0-or-later AND LGPL-2.1-or-later"
 _gccrel=$pkgver-r$pkgrel
-depends="binutils-x86 mpc1"
+depends="binutils-armhf mpc1"
 makedepends_build="gcc g++ bison flex texinfo gawk zip gmp-dev mpfr-dev mpc1-dev zlib-dev"
-makedepends_host="linux-headers gmp-dev mpfr-dev mpc1-dev isl-dev zlib-dev musl-dev-x86 binutils-x86"
-subpackages="g++-x86:gpp libstdc++-dev-x86:libcxx_dev"
+makedepends_host="linux-headers gmp-dev mpfr-dev mpc1-dev isl-dev zlib-dev musl-dev-armhf binutils-armhf"
+subpackages="g++-armhf:gpp libstdc++-dev-armhf:libcxx_dev"
 [ "$CHOST" = "$CTARGET" ] && subpackages="gcc-gdb gcc-doc$_target"
 replaces="libstdc++ binutils"
 
@@ -268,13 +268,9 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+	0035-Fix-ICE-observed-in-PR110280.patch
 	"
 
-# secfixes:
-#   13.2.1_git20231014-r0:
-#     - CVE-2023-4039
-
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -787,7 +783,7 @@ gdb() {
 }
 
 sha512sums="
-406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
+284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -822,5 +818,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
 "

cross/gcc-armv7/0035-Fix-ICE-observed-in-PR110280.patch

@@ -0,0 +1,61 @@
+From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
+From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+Date: Fri, 23 Jun 2023 15:27:17 +0530
+Subject: [PATCH 35/35] Fix ICE observed in PR110280.
+
+gcc/ChangeLog:
+	PR tree-optimization/110280
+	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
+	using build_vector_from_val with the element of input operand, and
+	mask's type if operand and mask's types don't match.
+
+gcc/testsuite/ChangeLog:
+	PR tree-optimization/110280
+	* gcc.target/aarch64/sve/pr110280.c: New test.
+---
+ gcc/match.pd                                    |  9 ++++++++-
+ gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
+ 2 files changed, 20 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+
+diff --git a/gcc/match.pd b/gcc/match.pd
+index 91182448250..c3bb4fbc0a7 100644
+--- a/gcc/match.pd
++++ b/gcc/match.pd
+@@ -8292,7 +8292,14 @@ and,
+ 
+ (simplify
+  (vec_perm vec_same_elem_p@0 @0 @1)
+- @0)
++ (if (types_match (type, TREE_TYPE (@0)))
++  @0
++  (with
++   {
++     tree elem = uniform_vector_p (@0);
++   }
++   (if (elem)
++    { build_vector_from_val (type, elem); }))))
+ 
+ /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
+ (simplify
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+new file mode 100644
+index 00000000000..d3279f38362
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fdump-tree-optimized" } */
++
++#include "arm_sve.h"
++
++svuint32_t l()
++{
++  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
++  return svld1rq_u32(svptrue_b8(), lanes);
++}
++
++/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
+-- 
+2.41.0
+

cross/gcc-armv7/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-armv7/APKBUILD

@@ -24,8 +24,8 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-armv7
-pkgver=13.2.1_git20231014
-# i.e. 13.2.1, must match gcc/BASE-VER
+pkgver=13.1.1_git20230722
+# i.e. 13.1.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armv7
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for armv7"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -268,13 +268,9 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+	0035-Fix-ICE-observed-in-PR110280.patch
 	"
 
-# secfixes:
-#   13.2.1_git20231014-r0:
-#     - CVE-2023-4039
-
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -787,7 +783,7 @@ gdb() {
 }
 
 sha512sums="
-406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
+284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -822,5 +818,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
 "

cross/gcc-riscv64/0035-Fix-ICE-observed-in-PR110280.patch

@@ -0,0 +1,61 @@
+From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
+From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+Date: Fri, 23 Jun 2023 15:27:17 +0530
+Subject: [PATCH 35/35] Fix ICE observed in PR110280.
+
+gcc/ChangeLog:
+	PR tree-optimization/110280
+	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
+	using build_vector_from_val with the element of input operand, and
+	mask's type if operand and mask's types don't match.
+
+gcc/testsuite/ChangeLog:
+	PR tree-optimization/110280
+	* gcc.target/aarch64/sve/pr110280.c: New test.
+---
+ gcc/match.pd                                    |  9 ++++++++-
+ gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
+ 2 files changed, 20 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+
+diff --git a/gcc/match.pd b/gcc/match.pd
+index 91182448250..c3bb4fbc0a7 100644
+--- a/gcc/match.pd
++++ b/gcc/match.pd
+@@ -8292,7 +8292,14 @@ and,
+ 
+ (simplify
+  (vec_perm vec_same_elem_p@0 @0 @1)
+- @0)
++ (if (types_match (type, TREE_TYPE (@0)))
++  @0
++  (with
++   {
++     tree elem = uniform_vector_p (@0);
++   }
++   (if (elem)
++    { build_vector_from_val (type, elem); }))))
+ 
+ /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
+ (simplify
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+new file mode 100644
+index 00000000000..d3279f38362
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fdump-tree-optimized" } */
++
++#include "arm_sve.h"
++
++svuint32_t l()
++{
++  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
++  return svld1rq_u32(svptrue_b8(), lanes);
++}
++
++/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
+-- 
+2.41.0
+

cross/gcc-riscv64/APKBUILD

@@ -1,8 +1,8 @@
 # Automatically generated aport, do not edit!
-# Generator: pmbootstrap aportgen gcc-x86_64
+# Generator: pmbootstrap aportgen gcc-riscv64
 # Based on: main/gcc (from Alpine)
 
-CTARGET_ARCH=x86_64
+CTARGET_ARCH=riscv64
 CTARGET="$(arch_to_hostspec ${CTARGET_ARCH})"
 LANG_D=false
 LANG_OBJC=false
@@ -23,9 +23,9 @@ CBUILDROOT="/"
 
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
-pkgname=gcc-x86_64
-pkgver=13.2.1_git20231014
-# i.e. 13.2.1, must match gcc/BASE-VER
+pkgname=gcc-riscv64
+pkgver=13.1.1_git20230722
+# i.e. 13.1.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -33,17 +33,17 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CBUILD" != "$CHOST" ] && _cross="-$CARCH" || _cross=""
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
-pkgname=gcc-x86_64
-pkgrel=0
-pkgdesc="Stage2 cross-compiler for x86_64"
+pkgname=gcc-riscv64
+pkgrel=2
+pkgdesc="Stage2 cross-compiler for riscv64"
 url="https://gcc.gnu.org"
-arch="aarch64"
+arch="x86_64"
 license="GPL-2.0-or-later AND LGPL-2.1-or-later"
 _gccrel=$pkgver-r$pkgrel
-depends="binutils-x86_64 mpc1"
+depends="binutils-riscv64 mpc1"
 makedepends_build="gcc g++ bison flex texinfo gawk zip gmp-dev mpfr-dev mpc1-dev zlib-dev"
-makedepends_host="linux-headers gmp-dev mpfr-dev mpc1-dev isl-dev zlib-dev musl-dev-x86_64 binutils-x86_64"
-subpackages="g++-x86_64:gpp libstdc++-dev-x86_64:libcxx_dev"
+makedepends_host="linux-headers gmp-dev mpfr-dev mpc1-dev isl-dev zlib-dev musl-dev-riscv64 binutils-riscv64"
+subpackages="g++-riscv64:gpp libstdc++-dev-riscv64:libcxx_dev"
 [ "$CHOST" = "$CTARGET" ] && subpackages="gcc-gdb gcc-doc$_target"
 replaces="libstdc++ binutils"
 
@@ -268,13 +268,9 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+	0035-Fix-ICE-observed-in-PR110280.patch
 	"
 
-# secfixes:
-#   13.2.1_git20231014-r0:
-#     - CVE-2023-4039
-
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -787,7 +783,7 @@ gdb() {
 }
 
 sha512sums="
-406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
+284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -822,5 +818,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
+048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
 "

cross/gcc-x86/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-x86_64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc4-aarch64/01_all_gcc49_configure.patch

@@ -0,0 +1,156 @@
+2013-12-30  Magnus Granberg <zorry@gentoo.org>
+
+	* gcc/configure.ac		Add --enable-esp and define ENABLE_ESP.
+	Check if we support crtbeginP and define ENABLE_CRTBEGINP.
+	* gcc/configure	Regenerated
+
+
+--- a/gcc/configure.ac	2011-11-18 11:52:32.000000000 +0100
++++ b/gcc/configure.ac	2012-10-02 17:39:15.649526241 +0200
+@@ -5130,6 +5237,55 @@ if test x"${LINKER_HASH_STYLE}" != x; th
+                                          [The linker hash style])
+ fi
+ 
++# --------------
++# Esp checks
++# --------------
++
++# Check whether --enable-esp was given and target have the support.
++AC_ARG_ENABLE([esp],
++[AS_HELP_STRING([--enable-esp],
++               [Enable Stack protector and Position independent executable as
++                default if we have suppot for it when compiling
++                and link with -z now as default.
++                Linux targets supported i*86, x86_64, x32,
++                powerpc, powerpc64, ia64, arm and mips.])],
++  enable_esp=$enableval,
++  enable_esp=no)
++if test $enable_esp = yes ; then
++  AC_MSG_CHECKING(if $target support esp)
++  case "$target" in
++    i?86*-*-linux* | x86_64-*-linux* | powerpc*-*-linux* | mips-*-linux* | arm*-*-linux* | ia64-*-linux*)
++      enable_esp=yes
++      AC_DEFINE(ENABLE_ESP, 1,
++        [Define if your target support esp and you have enable it.])
++      ;;
++    *)
++      enable_esp=no
++      ;;
++  esac
++AC_MSG_RESULT($enable_esp)
++fi
++AC_SUBST([enable_esp])
++if test $enable_esp = yes ; then
++  AC_MSG_CHECKING(checking for crtbeginP.o support)
++    if test x$enable_esp = xyes ; then
++      case "$target" in
++        ia64*-*-linux*)
++          enable_crtbeginP=no ;;
++        *-*-linux*)
++          if test x$gcc_cv_ld_pie = xyes && test x$lt_cv_prog_compiler_static_works = xyes; then
++            enable_crtbeginP=yes
++            AC_DEFINE(ENABLE_CRTBEGINP, 1,
++              [Define if your compiler will support crtbeginP.])
++          fi
++          ;;
++        *) enable_crtbeginP=no ;;
++      esac
++    fi
++  AC_MSG_RESULT($enable_crtbeginP)
++fi
++AC_SUBST([enable_crtbeginP])
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 
+--- a/gcc/configure	2013-02-01 21:26:24.000000000 +0100
++++ b/gcc/configure	2013-02-12 01:59:20.000000000 +0100
+@@ -600,6 +600,8 @@
+ ac_subst_vars='LTLIBOBJS
+ LIBOBJS
+ PICFLAG
++enable_crtbeginP
++enable_esp
+ enable_host_shared
+ enable_plugin
+ pluginlibs
+@@ -920,6 +922,7 @@
+ enable_plugin
+ enable_libquadmath_support
+ with_linker_hash_style
++enable_esp
+ '
+       ac_precious_vars='build_alias
+ host_alias
+@@ -1633,6 +1636,11 @@
+   --enable-plugin         enable plugin support
+   --disable-libquadmath-support
+                           disable libquadmath support for Fortran
++  --enable-esp            Enable Stack protector and Position independent
++                          executable as default if we have suppot for it when
++                          compiling and link with -z now as default.
++                          Linux targets supported i*86, x86_64, x32,
++                          powerpc, powerpc64, ia64, arm and mips.
+ 
+ Optional Packages:
+   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+@@ -27419,6 +27427,59 @@
+ 
+ fi
+ 
++# --------------
++# Esp checks
++# --------------
++
++# Check whether --enable-esp was given and target have the support.
++# Check whether --enable-esp was given.
++if test "${enable_esp+set}" = set; then :
++  enableval=$enable_esp; enable_esp=$enableval
++else
++  enable_esp=no
++fi
++
++if test $enable_esp = yes ; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $target support esp" >&5
++$as_echo_n "checking if $target support esp... " >&6; }
++  case "$target" in
++    i?86*-*-linux* | x86_64-*-linux* | powerpc*-*-linux* | mips*-*-linux* | arm*-*-linux* | ia64-*-linux*)
++      enable_esp=yes
++
++$as_echo "#define ENABLE_ESP 1" >>confdefs.h
++
++      ;;
++    *)
++      enable_esp=no
++      ;;
++  esac
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_esp" >&5
++$as_echo "$enable_esp" >&6; }
++fi
++
++if test $enable_esp = yes ; then
++  { $as_echo "$as_me:${as_lineno-$LINENO}: checking checking for crtbeginP.o support" >&5
++$as_echo_n "checking checking for crtbeginP.o support... " >&6; }
++    if test x$enable_esp = xyes ; then
++      case "$target" in
++        ia64*-*-linux*)
++          enable_crtbeginP=no ;;
++        *-*-linux*)
++          if test x$gcc_cv_ld_pie = xyes && test x$lt_cv_prog_compiler_static_works = xyes; then
++            enable_crtbeginP=yes
++
++$as_echo "#define ENABLE_CRTBEGINP 1" >>confdefs.h
++
++          fi
++          ;;
++        *) enable_crtbeginP=no ;;
++      esac
++    fi
++  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_crtbeginP" >&5
++$as_echo "$enable_crtbeginP" >&6; }
++fi
++
++
+ # Configure the subdirectories
+ # AC_CONFIG_SUBDIRS($subdirs)
+ 

cross/gcc4-aarch64/02_all_gcc48_config.in.patch

@@ -0,0 +1,32 @@
+2013-02-13	Magnus Granberg		<zorry@gentoo.org>
+
+		* gcc/config.in	Add ENABLE_CRTBEGINP, ENABLE_ESP
+
+--- ./gcc/config.in	2009-04-21 11:08:08.000000000 +0200
++++ ./gcc/config.in	2009-05-12 00:10:08.000000000 +0200
+@@ -46,6 +46,12 @@
+ #endif
+ 
+ 
++/* Define to 1 to enable crtbeginP.o. */
++#ifndef USED_FOR_TARGET
++#undef ENABLE_CRTBEGINP
++#endif
++
++
+ /* Define to 1 to specify that we are using the BID decimal floating point
+    format instead of DPD */
+ #ifndef USED_FOR_TARGET
+@@ -65,6 +65,12 @@
+ #endif
+ 
+ 
++/* Define to 1 to enable esp. */
++#ifndef USED_FOR_TARGET
++#undef ENABLE_ESP
++#endif
++
++
+ /* Define to 1 to enable fixed-point arithmetic extension to C. */
+ #ifndef USED_FOR_TARGET
+ #undef ENABLE_FIXED_POINT

cross/gcc4-aarch64/03_all_gcc49_Makefile.in.patch

@@ -0,0 +1,96 @@
+2012-01-17	Magnus Granberg		<zorry@gentoo.org>
+
+		* gcc/Makefile.in	Add -fno-PIE. to ALL_CFLAGS and
+			ALL_CXXFLAGS if enable_esp yes.
+			Echo enable_esp and enable_crtbeginP to tmp-libgcc.mvars.
+		* libgcc/Makefile.in	Add crtbeginP.o to EXTRA_PARTS if enable_crtbeginP yes
+			We add new file crtbeginP.o if enable_crtbeginP yes
+			Add -fno-PIE. to CRTSTUFF_CFLAGS.
+
+--- a/gcc/Makefile.in	2011-11-09 02:20:14.000000000 +0100
++++ b/gcc/Makefile.in	2011-12-24 22:28:08.864804375 +0100
+@@ -247,6 +247,14 @@ LINKER_FLAGS = $(CFLAGS)
+ endif
+ endif
+ 
++# We don't want to compile the compiler with -fPIE, it make PCH fail.
++enable_esp = @enable_esp@
++ifeq ($(enable_esp),yes)
++ESP_NOPIE_CFLAGS = -fno-PIE
++else
++ESP_NOPIE_CFLAGS=
++endif
++
+ # -------------------------------------------
+ # Programs which operate on the build machine
+ # -------------------------------------------
+@@ -974,12 +982,13 @@ INTERNAL_CFLAGS = -DIN_GCC @CROSS@
+ 
+ # This is the variable actually used when we compile. If you change this,
+ # you probably want to update BUILD_CFLAGS in configure.ac
+-ALL_CFLAGS = $(T_CFLAGS) $(CFLAGS-$@) \
++ALL_CFLAGS = $(ESP_NOPIE_CFLAGS) $(T_CFLAGS) $(CFLAGS-$@) \
+   $(CFLAGS) $(INTERNAL_CFLAGS) $(COVERAGE_FLAGS) $(WARN_CFLAGS) @DEFS@
+ 
+ # The C++ version.
+-ALL_CXXFLAGS = $(T_CFLAGS) $(CFLAGS-$@) $(CXXFLAGS) $(INTERNAL_CFLAGS) \
+-  $(COVERAGE_FLAGS) $(NOEXCEPTION_FLAGS) $(WARN_CXXFLAGS) @DEFS@
++ALL_CXXFLAGS = $(ESP_NOPIE_CFLAGS) $(T_CFLAGS) $(CFLAGS-$@) $(CXXFLAGS) \
++  $(INTERNAL_CFLAGS) $(COVERAGE_FLAGS) $(NOEXCEPTION_FLAGS) \
++  $(WARN_CXXFLAGS) @DEFS@
+ 
+ # Likewise.  Put INCLUDES at the beginning: this way, if some autoconf macro
+ # puts -I options in CPPFLAGS, our include files in the srcdir will always
+@@ -1814,6 +1823,8 @@ libgcc.mvars: config.status Makefile spe
+ 	echo GCC_CFLAGS = '$(GCC_CFLAGS)' >> tmp-libgcc.mvars
+ 	echo INHIBIT_LIBC_CFLAGS = '$(INHIBIT_LIBC_CFLAGS)' >> tmp-libgcc.mvars
+ 	echo TARGET_SYSTEM_ROOT = '$(TARGET_SYSTEM_ROOT)' >> tmp-libgcc.mvars
++	echo enable_esp = '$(enable_esp)' >> tmp-libgcc.mvars
++	echo enable_crtbeginP = '@enable_crtbeginP@' >> tmp-libgcc.mvars
+ 
+ 	mv tmp-libgcc.mvars libgcc.mvars
+ 
+--- a/libgcc/Makefile.in	2011-11-22 04:01:02.000000000 +0100
++++ b/libgcc/Makefile.in	2011-12-25 15:18:22.449610631 +0100
+@@ -219,6 +219,17 @@ else
+ DECNUMINC =
+ endif
+ 
++ifeq ($(enable_esp),yes)
++ESP_NOPIE_CFLAGS = -fno-PIE
++else
++ESP_NOPIE_CFLAGS=
++endif
++
++# We add crtbeginP.o to the EXTRA_PARTS list if enable_crtbeginP = yes
++ifeq ($(enable_crtbeginP),yes)
++EXTRA_PARTS += crtbeginP.o
++endif
++
+ # Options to use when compiling libgcc2.a.
+ #
+ LIBGCC2_DEBUG_CFLAGS = -g
+@@ -279,7 +290,7 @@ INTERNAL_CFLAGS = $(CFLAGS) $(LIBGCC2_CF
+ CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
+   -finhibit-size-directive -fno-inline -fno-exceptions \
+   -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \
+-  -fno-stack-protector \
++  -fno-stack-protector $(ESP_NOPIE_CFLAGS) \
+   $(INHIBIT_LIBC_CFLAGS)
+ 
+ # Extra flags to use when compiling crt{begin,end}.o.
+@@ -966,6 +977,13 @@ crtendS$(objext): $(srcdir)/crtstuff.c
+ # This is a version of crtbegin for -static links.
+ crtbeginT$(objext): $(srcdir)/crtstuff.c
+ 	$(crt_compile) $(CRTSTUFF_T_CFLAGS) -c $< -DCRT_BEGIN -DCRTSTUFFT_O
++
++# This is a version of crtbegin for -static -fPIE links.
++ifeq ($(enable_crtbeginP),yes)
++crtbeginP$(objext): $(srcdir)/crtstuff.c
++	$(crt_compile) $(CRTSTUFF_T_CFLAGS_S) \
++	  -c $< -DCRT_BEGIN -DCRTSTUFFT_O -DCRTSTUFFS_O
++endif
+ 
+ ifeq ($(enable_vtable_verify),yes)
+ # These are used in vtable verification; see comments in source files for
+ 

cross/gcc4-aarch64/05_all_gcc48_gcc.c.patch

@@ -0,0 +1,25 @@
+2013-03-24	Magnus Granberg		<zorry@gentoo.org>
+
+		* gcc/gcc.c								include esp.h
+		static const char *cc1_spec 			We set that in esp.h if ENABLE_ESP.
+
+--- ./gcc/gcc.c	2010-01-21 10:29:30.000000000 -0500
++++ ./gcc/gcc.c	2010-01-29 23:29:16.000000000 -0500
+@@ -44,6 +44,7 @@
+ #include "opts.h"
+ #include "params.h"
+ #include "vec.h"
++#include "config/esp.h" /* for --enable-esp support */
+ #include "filenames.h"
+ 
+ /* By default there is no special suffix for target executables.  */
+@@ -822,7 +823,9 @@
+ 
+ static const char *asm_debug;
+ static const char *cpp_spec = CPP_SPEC;
++#ifndef ENABLE_ESP
+ static const char *cc1_spec = CC1_SPEC;
++#endif
+ static const char *cc1plus_spec = CC1PLUS_SPEC;
+ static const char *link_gcc_c_sequence_spec = LINK_GCC_C_SEQUENCE_SPEC;
+ static const char *link_ssp_spec = LINK_SSP_SPEC;