temp/calls: fork to use sofia-sip-linphone

[ci:skip-vercheck]
temp/sofia-sip-linphone: new aport
2024-08-17 21:12:56 +02:00 · 2024-08-17 21:09:38 +02:00 · 2024-08-17 16:45:05 +02:00 · 2024-08-16 12:01:21 +09:00 · 2024-08-15 13:43:29 -07:00 · 2024-08-15 18:54:55 +02:00
82 changed files with 7676 additions and 234 deletions
@@ -81,6 +81,9 @@ update_linux_next() {
 	# Update the checksums
 	pmbootstrap checksum linux-next

+	# Ensure it builds
+	pmbootstrap build --details-to-stdout linux-next
+
 	# Commit
 	git add device/testing/linux-next/APKBUILD
 	git commit -S -m "linux-next: upgrade to $latest"
@@ -17,7 +17,7 @@ def check_kconfig(pkgnames):
        pkgname = pkgnames[i]
        print(f"  ({i+1}/{len(pkgnames)}) {pkgname}")

-        p = subprocess.run(["pmbootstrap", "kconfig", "check", pkgname],
+        p = subprocess.run(["pmbootstrap", "kconfig", "check", "--keep-going", pkgname],
                           check=False)

        if p.returncode:
@@ -27,7 +27,7 @@ def check_kconfig(pkgnames):


 def check_kconfig_all():
-    p = subprocess.run(["pmbootstrap", "kconfig", "check"], check=False)
+    p = subprocess.run(["pmbootstrap", "kconfig", "check", "--keep-going"], check=False)
    return p.returncode == 0


@@ -174,6 +174,9 @@ build-riscv64:

 auto-update:
  stage: autoupdate
+  # We build packages before merging too
+  tags:
+    - saas-linux-large-amd64
  rules:
    # This variable is set in the scheduled pipeline configuration. It should be a space separated list of
    # package names to update.
@@ -28,7 +28,6 @@
 -->
 * [ ] edge (`master` branch)
 * [ ] `v24.06`
-* [ ] `v23.12` (supported until 2024-07-16)

 * [ ] I confirm that the issue still is present after running `sudo apk upgrade -a`

@@ -94,6 +94,7 @@ device/*/kobo-epdc-extractor/			@akemnade
 device/*/linux-google-nyan/			@jenneron
 device/*/linux-google-veyron/			@jenneron
 device/*/linux-huawei-plank/			@gtrxAC
+device/*/linux-next/				@calebccff
 device/*/linux-postmarketos-allwinner/		@Arnavion @PsychoGame
 device/*/linux-postmarketos-amlogic/		@funderscore @exkc
 device/*/linux-postmarketos-exynos4/		@Newbyte @Grimler @knuxify
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""

 pkgname=gcc-aarch64
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for aarch64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"

 # secfixes:
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "
@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
+/* Like simplify_gen_subreg, but force OP into a new register if the
+   subreg cannot be formed directly.  */
+
+rtx
+force_subreg (machine_mode outermode, rtx op,
+	      machine_mode innermode, poly_uint64 byte)
+{
+  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (x)
+    return x;
+
+  op = copy_to_mode_reg (innermode, op);
+  return simplify_gen_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
+      /* Make sure that the relationship between the two subregs is
+	 known at compile time.  */
+      if (!ordered_p (outersize, innermostsize))
+	return NULL_RTX;
+
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl)
+{
+    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
+}
+
+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
+     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
+    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
+	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
+    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
+    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
+{
+    return svset_neonq_u16 (a, permute_tbl.val[1]);
+}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+		      machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""

 pkgname=gcc-armhf
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for armhf"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"

 # secfixes:
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "
@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
+/* Like simplify_gen_subreg, but force OP into a new register if the
+   subreg cannot be formed directly.  */
+
+rtx
+force_subreg (machine_mode outermode, rtx op,
+	      machine_mode innermode, poly_uint64 byte)
+{
+  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (x)
+    return x;
+
+  op = copy_to_mode_reg (innermode, op);
+  return simplify_gen_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
+      /* Make sure that the relationship between the two subregs is
+	 known at compile time.  */
+      if (!ordered_p (outersize, innermostsize))
+	return NULL_RTX;
+
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl)
+{
+    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
+}
+
+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
+     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
+    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
+	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
+    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
+    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
+{
+    return svset_neonq_u16 (a, permute_tbl.val[1]);
+}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+		      machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""

 pkgname=gcc-armv7
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for armv7"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"

 # secfixes:
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "
@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
+/* Like simplify_gen_subreg, but force OP into a new register if the
+   subreg cannot be formed directly.  */
+
+rtx
+force_subreg (machine_mode outermode, rtx op,
+	      machine_mode innermode, poly_uint64 byte)
+{
+  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (x)
+    return x;
+
+  op = copy_to_mode_reg (innermode, op);
+  return simplify_gen_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
+      /* Make sure that the relationship between the two subregs is
+	 known at compile time.  */
+      if (!ordered_p (outersize, innermostsize))
+	return NULL_RTX;
+
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl)
+{
+    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
+}
+
+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
+     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
+    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
+	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
+    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
+    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
+{
+    return svset_neonq_u16 (a, permute_tbl.val[1]);
+}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+		      machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""

 pkgname=gcc-riscv64
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for riscv64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"

 # secfixes:
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "
@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
+/* Like simplify_gen_subreg, but force OP into a new register if the
+   subreg cannot be formed directly.  */
+
+rtx
+force_subreg (machine_mode outermode, rtx op,
+	      machine_mode innermode, poly_uint64 byte)
+{
+  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (x)
+    return x;
+
+  op = copy_to_mode_reg (innermode, op);
+  return simplify_gen_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
+      /* Make sure that the relationship between the two subregs is
+	 known at compile time.  */
+      if (!ordered_p (outersize, innermostsize))
+	return NULL_RTX;
+
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl)
+{
+    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
+}
+
+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
+     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
+    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
+	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
+    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
+    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
+{
+    return svset_neonq_u16 (a, permute_tbl.val[1]);
+}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+		      machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""

 pkgname=gcc-x86
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for x86"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"

 # secfixes:
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "
@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
+/* Like simplify_gen_subreg, but force OP into a new register if the
+   subreg cannot be formed directly.  */
+
+rtx
+force_subreg (machine_mode outermode, rtx op,
+	      machine_mode innermode, poly_uint64 byte)
+{
+  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (x)
+    return x;
+
+  op = copy_to_mode_reg (innermode, op);
+  return simplify_gen_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
+      /* Make sure that the relationship between the two subregs is
+	 known at compile time.  */
+      if (!ordered_p (outersize, innermostsize))
+	return NULL_RTX;
+
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl)
+{
+    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
+}
+
+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
+     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
+    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
+	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
+    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
+    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
+{
+    return svset_neonq_u16 (a, permute_tbl.val[1]);
+}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+		      machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""

 pkgname=gcc-x86_64
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for x86_64"
 url="https://gcc.gnu.org"
 arch="aarch64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"

 # secfixes:
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "
@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
+/* Like simplify_gen_subreg, but force OP into a new register if the
+   subreg cannot be formed directly.  */
+
+rtx
+force_subreg (machine_mode outermode, rtx op,
+	      machine_mode innermode, poly_uint64 byte)
+{
+  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
+  if (x)
+    return x;
+
+  op = copy_to_mode_reg (innermode, op);
+  return simplify_gen_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
+extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
+      /* Make sure that the relationship between the two subregs is
+	 known at compile time.  */
+      if (!ordered_p (outersize, innermostsize))
+	return NULL_RTX;
+
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl)
+{
+    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
+}
+
+/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
+      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
+     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
+				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
+			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
+    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
+	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
+	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
+					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
+    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
+      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
+	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
+      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
+				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
+    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
+  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
+/* { dg-options "-O2" } */
+
+#include <arm_neon.h>
+#include <arm_sve.h>
+#include <arm_neon_sve_bridge.h>
+
+svuint16_t
+convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
+{
+    return svset_neonq_u16 (a, permute_tbl.val[1]);
+}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
+++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
+/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
+   which has mode INNERMODE.  Allow OP to be forced into a new register
+   if necessary.
+
+   Return null on failure.  */
+
+rtx
+force_lowpart_subreg (machine_mode outermode, rtx op,
+		      machine_mode innermode)
+{
+  auto byte = subreg_lowpart_offset (outermode, innermode);
+  return force_subreg (outermode, op, innermode, byte);
+}
+
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
+++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
+extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
+      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+
@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-gru
 pkgdesc="Google Gru Chromebooks"
-pkgver=6
+pkgver=7
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -53,6 +53,6 @@ nonfree_firmware() {


 sha512sums="
-6a8aba7e13f864a223a658f724ad8ff6c04ed986a747439cf88a6365c5fa037da9fb4950fa94794eff64937979f988015af9d0a6359deb041d1a2b128baac75e  deviceinfo
+7815e3a164720b5ad0df7ce8d12b12fe85cc4bb7bf4a09ccc0eb831a58a920026fd92d545f4d6fb459a688e15b9d542e360fd597cd5d3b01a3ea338c3928d2a3  deviceinfo
 a750a0c41068082e0b82351d5aec91715e1a5215b09b26fec644dfe259cea2d662e878433a732a8c06dab2a9b420baec2bcc6161d8357cf3ed770239c5165090  modules-initfs
 "
@@ -25,5 +25,6 @@ deviceinfo_cgpt_kpart="/boot/vmlinuz.kpart"
 deviceinfo_cgpt_kpart_start="8192"
 deviceinfo_cgpt_kpart_size="65536"
 deviceinfo_depthcharge_board="gru"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
 deviceinfo_generate_extlinux_config="true"
@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-kukui
 pkgdesc="Google Kukui Chromebooks"
-pkgver=7
+pkgver=8
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -14,7 +14,6 @@ depends="
 	linux-postmarketos-mediatek-mt8183>=6.1.28-r0
 	postmarketos-base
 	postmarketos-cros-common
-	postmarketos-initramfs-minimal
 	soc-mediatek-mt8183
 "
 makedepends="devicepkg-dev"
@@ -74,6 +73,6 @@ nonfree_firmware() {
 }

 sha512sums="
-e1c88545563aa40b69f79ed1d86b4da0d7ad65dfff07dce05f56d51b442ad9bae27ae2d27afa2f5131309072a9ea4f3b026d498ab067b315ed0719a3dded4b2c  deviceinfo
+ecd503069ecf272ddc238bd49dc257a1f3e0f4c20b322238e2da83104b94b331c22886d1591b6fe0b78c986e15ac6251e364ec1b750f9125ea722a6b1a79e2b8  deviceinfo
 8e95624610dae7d18684056396c9e82635ddce7303d6770e965f9372ffa101fdfd5f8337bc7368004890e9836798663a98c142c52ed63795877ea37ac8da56af  modules-initfs
 "
@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="65536"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8183"
 # board here.
 deviceinfo_depthcharge_board="mt8183"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
@@ -3,7 +3,7 @@
 # Co-Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-oak
 pkgdesc="Google Oak Chromebooks"
-pkgver=5
+pkgver=6
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -40,6 +40,6 @@ nonfree_firmware() {
 }

 sha512sums="
-ebf7ed07ffcfe30c01c717db00c255e2c650339bace70afffcac4566267da8b6d3e22f819601be2ee355d2c1f56b01e37fca5566a2517fc1ffb642e530b674fb  deviceinfo
+d082e6c155347f662403f611f44c3eddb2a0548397bec4f29b882f371a18efa9c2628a88599b19c0c58c1886d0c25035367f02651a60fb6c3293faa1449b83d5  deviceinfo
 4b0197eacfeeb4b13f5abc26950f570ee762742547674ce10110ccea63eb46630a2e3b5f87e9c9a1f9deda21baf05bec248ab7a65656687ec94d296b5657dafa  modules-initfs
 "
@@ -33,4 +33,5 @@ deviceinfo_cgpt_kpart_size="65536"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8173"
 # board here.
 deviceinfo_depthcharge_board="mt8173"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-trogdor
 pkgdesc="Google Trogdor Chromebooks"
-pkgver=2
+pkgver=3
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -44,6 +44,6 @@ nonfree_firmware() {


 sha512sums="
-e2eee558c89272358b4531ef9d7b7cefc937702c17985c3067181029a7f2c8545f68c3634d515fee6d12229d09f52b6f2b4ae804449f37c11b3aa9e5bcfaaced  deviceinfo
+0a40c43eda1dbb159da59c00b3a1e51fff299a29add210de4d9a16c060da523c358b6d821aa1dd16523bb912d00e1a1837193cce52415f329ac2e171d220f6d3  deviceinfo
 ef0257928f28aff25e6c625fabfd0942b01d4d86f1b523212ca825cf80f8b7a6c20ff17bfb02cb19f2a5d8787326ba22ad560a957c8d3c38b9ec70f1e16f9117  modules-initfs
 "
@@ -33,4 +33,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "qc7180"
 # board here.
 deviceinfo_depthcharge_board="qc7180"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
@@ -2,7 +2,7 @@

 pkgname=firmware-shift-sdm845
 pkgver=20240517
-pkgrel=0
+pkgrel=1
 pkgdesc="Firmware for SHIFT sdm845 devices"
 url="https://gitlab.com/sdm845-mainline/firmware-shift-sdm845"
 arch="aarch64"
@@ -33,8 +33,8 @@ package() {
 	done < "$srcdir/firmware.files"

 	# Install symlinks for using upstream firmware
-	ln -s ../mba.mbn "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/mba.mbn
-	ln -s ../../../ath10k/WCN3990/hw1.0/wlanmdsp.mbn "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/wlanmdsp.mbn
+	ln -s ../mba.mbn.zst "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/mba.mbn.zst
+	ln -s ../../../ath10k/WCN3990/hw1.0/wlanmdsp.mbn.zst "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/wlanmdsp.mbn.zst
 }

 pmtest() {
@@ -4,8 +4,8 @@
 # Kernel config based on: arch/arm/configs/exynos_defconfig

 pkgname=linux-postmarketos-exynos4
-pkgver=6.7.6
-pkgrel=6
+pkgver=6.10.0
+pkgrel=0
 pkgdesc="Mainline kernel fork for Samsung Exynos4 devices"
 arch="armv7"
 _carch="arm"
@@ -41,23 +41,11 @@ _tag="v${pkgver//_/-}-exynos4"
 source="
 	$pkgname-$_tag.tar.bz2::$url/-/archive/$_tag/linux-$_tag.tar.bz2
 	$_config
-	initramfs.list
-	init
-	tab3-limit-memory.patch
 "
 builddir="$srcdir/linux-$_tag"

-prepare_isorec() {
-	# https://wiki.postmarketos.org/wiki/Boot_process#isorec
-	cp -v /usr/$(arch_to_hostspec $arch)/bin/busybox.static \
-		"$builddir"/usr/
-	cp -v "$srcdir"/init "$builddir"/usr/
-	cp -v "$srcdir"/initramfs.list "$builddir"/usr/
-}
-
 prepare() {
 	default_prepare
-	prepare_isorec
 	cp -v "$srcdir/$_config" .config
 }

@@ -81,9 +69,6 @@ package() {
 }

 sha512sums="
-705cd617d135900cb25c8b6da7177d507e6a179b521e04aeae18080995514cbd69381a21f942ebf4d8cee427e3c60d53e6a06ed918ddcaacc243ca585ef61c11  linux-postmarketos-exynos4-v6.7.6-exynos4.tar.bz2
-4de127f68b56c380455f77610fcd6b0fd2ed8b79355fa9050ac90b0b2a9d5ad9fe3f5e81f304f8e3327e0203866ded2d6eae083847670eaa9fbdb156b50db9b8  config-postmarketos-exynos4.armv7
-aaff0332b90e1f9f62de1128cace934717336e54ab09de46477369fa808302482d97334e43a85ee8597c1bcab64d3484750103559fea2ce8cd51776156bf7591  initramfs.list
-09f1f214a24300696809727a7b04378887c06ca6f40803ca51a12bf2176a360b2eb8632139d6a0722094e05cb2038bdb04018a1e3d33fc2697674552ade03bee  init
-aea665e80dee318ec3be23d3f28b88e87eb551d2756e14d896781a0861a4387920f6969990eb171e8c7d6f86c36cef63a89337d63bfee7e44b9de7a8efb36c73  tab3-limit-memory.patch
+a320d0be4532f469be015e2a6706e507e89daaa55ad50d57a56451dca04b6bbea56f62d15877ef000027ce887ecd04257f9c71d7c9d80aab55607494205fa5c7  linux-postmarketos-exynos4-v6.10.0-exynos4.tar.bz2
+2dc3a1d57bf485b513308362b263de59dd4ee507f9a23935a91f7bee9fb119a172089b5b64b364a770e378e225e253424eacad6905e9f1be57231d4ed5cf7b9f  config-postmarketos-exynos4.armv7
 "
@@ -1,20 +0,0 @@
-#!/bin/busybox sh
-
-# Samsung kernels come with their own initramfs, which extract and load another
-# initramfs. Usually that depends on the recovery key combination being pressed
-# or not. For simplicity, we always boot the recovery image (from the recovery
-# partition) here.
-echo "### isorec initramfs ###"
-busybox mount -t proc proc /proc
-busybox mount -t sysfs sysfs /sys
-
-# always use the "isorec"-style lzop compressed initramfs
-# from the recovery partition
-load_image=/isorec.cpio
-busybox lzop -dc /dev/block/mmcblk0p6 > ${load_image}
-busybox cpio -iu < ${load_image}
-busybox rm ${load_image}
-
-busybox umount /sys
-busybox umount /proc
-exec /init
@@ -1,21 +0,0 @@
-dir /dev 755 0 0
-dir /dev/block 755 0 0
-nod /dev/block/mmcblk0 600 0 0 b 179 0
-nod /dev/block/mmcblk0p1 600 0 0 b 179 1
-nod /dev/block/mmcblk0p2 600 0 0 b 179 2
-nod /dev/block/mmcblk0p3 600 0 0 b 179 3
-nod /dev/block/mmcblk0p4 600 0 0 b 179 4
-nod /dev/block/mmcblk0p5 600 0 0 b 179 5
-nod /dev/block/mmcblk0p6 600 0 0 b 179 6
-nod /dev/block/mmcblk0p7 600 0 0 b 179 7
-nod /dev/block/mmcblk0p8 600 0 0 b 179 8
-nod /dev/block/mmcblk0p9 600 0 0 b 179 9
-nod /dev/block/mmcblk0p10 600 0 0 b 179 10
-nod /dev/block/mmcblk0p11 600 0 0 b 179 11
-nod /dev/block/mmcblk0p12 600 0 0 b 179 12
-nod /dev/console 600 0 0 c 5 1
-dir /bin 755 0 0
-dir /proc 755 0 0
-dir /sys 755 0 0
-file /bin/busybox usr/busybox.static 755 0 0
-file /init usr/init 755 0 0
@@ -1,36 +0,0 @@
-From 57ae04aa40be1e83e2da2fdf92de749f694ea5f8 Mon Sep 17 00:00:00 2001
-From: Artur Weber <aweber.kernel@gmail.com>
-Date: Sat, 17 Feb 2024 12:34:46 +0100
-Link: https://gitlab.com/exynos4-mainline/linux/-/merge_requests/13
-Subject: [PATCH] ARM: dts: exynos4212-tab3: Limit usable memory range
-
-The stock bootloader on the Samsung Galaxy Tab 3 8.0 provides an
-incorrect available memory range over ATAG_MEM. Limit the usable
-memory in the DTS to prevent it from doing so, without having to
-disable ATAG support.
-
-Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
---
- arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
-index 87a1317f9220..996cd5cb0c07 100644
--- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
-+++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
-@@ -45,6 +45,12 @@ chosen {
- 		/* Default S-BOOT bootloader loads initramfs here */
- 		linux,initrd-start = <0x42000000>;
- 		linux,initrd-end = <0x42800000>;
-+
-+		/*
-+		 * S-BOOT provides incorrect memory size in bootloader;
-+		 * override it here
-+		 */
-+		linux,usable-memory-range = <0x40000000 0x3fc00000>;
- 	};
- 
- 	firmware@204f000 {
-- 
-2.44.0
-
@@ -4,7 +4,7 @@
 # Contributor: Clayton Craft <clayton@craftyguy.net>
 pkgname=linux-purism-librem5
 pkgver=6.6.40
-pkgrel=1
+pkgrel=2
 # NOTE: Don't forget to rebase the config! See prepare() for instructions.
 _purismrel=2
 # <kernel ver>.<purism kernel release>
@@ -90,5 +90,5 @@ package() {

 sha512sums="
 b16f6d040024d826d4ac7a33ad23137fafbf1ac7ac8adeef3fd80a80dc308b70cf572de6e4a451eb607b1d18ad58c03493108c7a1ff9b26fa2bd03a475002903  linux-purism-librem5-6.6.40pureos2.tar.gz
-2982f5950820153cef5167b2cfebff7310b682266fda67fa370cebb8b6a93877f331a0f0877b127fc5ad186a72c9e6ed8b181ceeb6eb9ce74a56a4e9e4805ad2  config-purism-librem5.aarch64
+8039685a22032bc5dcda9b2abfb16aac3bb5a5f416e66e39178a593dfef15a1526b3d513b3c4120332dc1b1b1f72e0a97f7303c495fe3a648067842b51911868  config-purism-librem5.aarch64
 "
@@ -2,9 +2,9 @@
 # Automatically generated file; DO NOT EDIT.
 # Linux/arm64 6.6.40 Kernel Configuration
 #
-CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 13.2.1_git20240309) 13.2.1 20240309"
+CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 14.2.0) 14.2.0"
 CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=130201
+CONFIG_GCC_VERSION=140200
 CONFIG_CLANG_VERSION=0
 CONFIG_AS_IS_GNU=y
 CONFIG_AS_VERSION=24200
@@ -13,7 +13,6 @@ CONFIG_LD_VERSION=24200
 CONFIG_LLD_VERSION=0
 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
 CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
-CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
 CONFIG_CC_HAS_ASM_INLINE=y
 CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
 CONFIG_PAHOLE_VERSION=0
@@ -4769,10 +4768,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
 # end of Console display driver support

-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO is not set
 # end of Graphics support

 # CONFIG_DRM_ACCEL is not set
@@ -0,0 +1,35 @@
+# Reference: <https://postmarketos.org/devicepkg>
+pkgname=device-amazon-tate
+pkgdesc="Amazon Kindle Fire HD (2nd Generation)"
+pkgver=1
+pkgrel=0
+url="https://postmarketos.org"
+license="MIT"
+arch="armv7"
+options="!check !archcheck"
+depends="
+	postmarketos-base
+	linux-amazon-tate
+	mkbootimg
+"
+makedepends="devicepkg-dev"
+source="
+	deviceinfo
+	initfs-hook.sh
+	amazon-omap-boot-hack.sh
+"
+
+build() {
+	devicepkg_build $startdir $pkgname
+}
+
+package() {
+	devicepkg_package $startdir $pkgname
+	install -Dm755 "$srcdir/amazon-omap-boot-hack.sh" "$pkgdir/usr/share/mkinitfs/amazon-omap-boot-hack.sh"
+}
+
+sha512sums="
+2e06c09046be664bbba5d55aafb06aceafbf41777bf116caa508d461190d546cc7ceae5160f0582dee20d88b5998837c00ffc3de928d1e5892bb32485523ce79  deviceinfo
+1aca985770246b9ca140996a498815b5c9ca3458a6cb84db85825344f01deda8b1de7c88e2e0c610df636ad2179faac7fd90d9992add51186a6449f2d43a3f71  initfs-hook.sh
+a5027ac9f113018d55e4c5fc065b0498d0a50df099a348fe38d6b841087aa285a8d67b400b9fe88007f41d0fd79c2fe69d62300af6963ecb40c5fb2353cbabf1  amazon-omap-boot-hack.sh
+"
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+echo "==> Amending boot.img for Amazon signature verification exploit"
+BOWSER_HEADER_DATA='\x50\x03\x00\x00\x00\x25\xe4\x00'
+BOWSER_HEADER_SIZE=1024
+BOWSER_HEADER_OFFSET=52
+tempfile=$(mktemp)
+bootimgfile=$(echo "${1}" | sed 's/initramfs/boot.img/g')
+dd if=/dev/zero of="${tempfile}" bs=$BOWSER_HEADER_SIZE count=1
+printf "%b" $BOWSER_HEADER_DATA | dd of="${tempfile}" bs=$BOWSER_HEADER_OFFSET seek=1 conv=notrunc
+cat "${bootimgfile}" >> "${tempfile}"
+mv "${tempfile}" "${bootimgfile}"
@@ -0,0 +1,39 @@
+# Reference: <https://postmarketos.org/deviceinfo>
+# Please use double quotes only. You can source this file in shell
+# scripts.
+
+deviceinfo_format_version="0"
+deviceinfo_name="Amazon Kindle Fire HD (2nd Generation)"
+deviceinfo_manufacturer="Amazon"
+deviceinfo_codename="amazon-tate"
+deviceinfo_year="2012"
+deviceinfo_arch="armv7"
+
+# Device related
+deviceinfo_gpu_accelerated="false"
+deviceinfo_chassis="tablet"
+deviceinfo_keyboard="false"
+deviceinfo_external_storage="false"
+deviceinfo_screen_width="800"
+deviceinfo_screen_height="1280"
+
+# Bootloader related
+deviceinfo_flash_method="fastboot"
+deviceinfo_kernel_cmdline="console=tty0 ignore_loglevel mem=1G init=/init"
+deviceinfo_generate_bootimg="true"
+deviceinfo_bootimg_qcdt="false"
+deviceinfo_bootimg_mtk_mkimage="false"
+deviceinfo_bootimg_dtb_second="false"
+deviceinfo_mkinitfs_postprocess="/usr/share/mkinitfs/amazon-omap-boot-hack.sh"
+deviceinfo_flash_offset_base="0x80000000"
+deviceinfo_flash_offset_kernel="0x00008000"
+deviceinfo_flash_offset_ramdisk="0x01000000"
+deviceinfo_flash_offset_second="0x00f00000"
+deviceinfo_flash_offset_tags="0x00000100"
+deviceinfo_flash_pagesize="2048"
+
+# Lab126, Inc.
+deviceinfo_usb_idVendor="0x1949"
+# Kindle
+deviceinfo_usb_idProduct="0x0007"
+
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+# Turn overlay0 off and on again to remove bootloader screen
+echo 0 > /sys/devices/platform/omapdss/overlay0/enabled
+echo 1 > /sys/devices/platform/omapdss/overlay0/enabled
@@ -2,7 +2,7 @@
 pkgname=device-asus-x00td
 pkgdesc="Asus ZenFone Max Pro M1"
 pkgver=1
-pkgrel=1
+pkgrel=2
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -32,7 +32,7 @@ kernel_downstream() {

 kernel_mainline() {
 	pkgdesc="Close to mainline; for kernel development only (most features aren't working)"
-	depends="linux-postmarketos-qcom-sdm660"
+	depends="linux-postmarketos-qcom-sdm660 soc-qcom-sdm660 soc-qcom-sdm660-rproc"
 	devicepkg_subpackage_kernel $startdir $pkgname $subpkgname
 }

@@ -2,8 +2,8 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-asurada
 pkgdesc="Google Asurada Chromebooks"
-pkgver=2
-pkgrel=1
+pkgver=3
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -35,6 +35,6 @@ nonfree_firmware() {
 }

 sha512sums="
-181faa71684361dbdcd49f2d16786ce8cd2366814f54a18c9e9caa989529ccc045713688d822a053959f88382a716622232276acf68d2f95597ac307ddf2240c  deviceinfo
+d497233fa521d67a04a87d6c1ca0c4360fc182856f9db1eff46f567127f258aa2516b1fbc4b0d1881f08204656b48b899becc7bdf6cbc6299dd6302505767495  deviceinfo
 d90b91bd2bb409941878ebadf8d28ef66406edb64cbcac99443c3e0c072801ba94ec9fa3b551f59b8a27a33c7a34f511604bd30328195fc261f927d87138801d  modules-initfs
 "
@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8192"
 # board here.
 deviceinfo_depthcharge_board="mt8192"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-cherry
 pkgdesc="Google Cherry Chromebooks"
-pkgver=2
+pkgver=3
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -35,6 +35,6 @@ nonfree_firmware() {
 }

 sha512sums="
-d69f5edb2dbc277561787306ea7fbb4cc4b1077a9385984e56bf38c24938630b17611fdb6e3c733b6a100b55256a266b60fba0adc0d952aaaaa2c2169d149007  deviceinfo
+6661b7c7a880dc3991921b1395ea48023a641b2d3f8e46d005b5778fed1bc5b5c0d55fa5d43499f00bb7453fde8d644ba3ae50d98de10f2daa62ad34bd1580c9  deviceinfo
 bb7f9a426bfa151c53089f07fd4e874b1fb69fd8180a584b4c9824e2d5ea1e7678602d74eb641b2640b692fec73b88acc78ca26ba9c9f3b8ac8366c6fb63dd5f  modules-initfs
 "
@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8195"
 # board here.
 deviceinfo_depthcharge_board="mt8195"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-corsola
 pkgdesc="Google Corsola Chromebooks"
-pkgver=3
+pkgver=4
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -40,7 +40,7 @@ nonfree_firmware() {
 	_dir="$subpkgdir/lib/firmware/mediatek/sof-tplg"
 	mkdir -p "$_dir"

-	ln -s sof-mt8186.tplg "$_dir"/sof-mt8186-google-steelix.tplg
+	ln -s sof-mt8186.tplg.zst "$_dir"/sof-mt8186-google-steelix.tplg.zst

 	# Alsa UCM configs
 	_ucm_files="
@@ -58,7 +58,7 @@ nonfree_firmware() {
 }

 sha512sums="
-924d60f2d921a9e22a34c945f55cb45c6c19245aeaec4993ae03fcafc91c1533632c61178f1836cbd11b581a26fa2bed5445e12f2ecccb4096a0ee33f7cb2772  deviceinfo
+2e00f2483bc135ececdc0e4428bab92798a1b43f7ddf6c6440d41313695bf2162ca56ab8931392e05a20aaf0b8dfd08d5f6c21e9bfbf3b734d06337bd8f254bb  deviceinfo
 56fdcaa7a610497ed1bddbbfc0850f895bcfd79173b2e7de4bcf196f69120e1b62680da2a0b74543f153cb3d2b84055e71e258e7df938913aff66dca47061d7a  modules-initfs
 d33545d435755c2cca3b916d920464f3f711c6f09f48b68622f740f389c4faf95544467d9e3b418e562fadb8141ae37f2311166f228d5149434183736710567d  alsa-ucm-conf-b728563a07ebcd05545c60989412ae023b1dd06d.tar.gz
 "
@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8186"
 # board here.
 deviceinfo_depthcharge_board="mt8186"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
@@ -0,0 +1,35 @@
+# Reference: <https://postmarketos.org/devicepkg>
+pkgname=device-lenovo-yoga-c630
+pkgdesc="Lenovo Yoga C630"
+pkgver=1
+pkgrel=0
+url="https://postmarketos.org"
+license="MIT"
+arch="aarch64"
+# pmb:strict: avoid grub-related install error during build with pmbootstrap
+options="!check !archcheck pmb:strict"
+depends="postmarketos-base
+	linux-postmarketos-qcom-sdm845
+	soc-qcom-sdm845
+	systemd-boot
+	firmware-lenovo-yoga-c630
+	soc-qcom-sdm845-nonfree-firmware
+"
+makedepends="devicepkg-dev"
+source="
+	deviceinfo
+	modules-initfs
+"
+
+build() {
+	devicepkg_build $startdir $pkgname
+}
+
+package() {
+	devicepkg_package $startdir $pkgname
+}
+
+sha512sums="
+c66907e00af107bb3130c48050e2209eb91213f5598b2ed92a828e678603b00d81fea776480041581f24a1d1c12a5b43bee7fa492068d1f1521440a0fb3aa195  deviceinfo
+490dd21b7775cea13e9dde9cb7568ddd204230fc786dad04dadee9b82b15749317fcf9c89286b4f73e8eeadd4bf19b5451f46d744d23f226d94e5bbbbc1692c3  modules-initfs
+"
@@ -0,0 +1,27 @@
+# Reference: <https://postmarketos.org/deviceinfo>
+# Please use double quotes only. You can source this file in shell scripts.
+
+deviceinfo_format_version="0"
+deviceinfo_name="Lenovo Yoga C630"
+deviceinfo_manufacturer="Lenovo"
+deviceinfo_codename="lenovo-yoga-c630"
+deviceinfo_arch="aarch64"
+deviceinfo_gpu_accelerated="true"
+
+deviceinfo_rootfs_image_sector_size="4096"
+
+# Device related
+deviceinfo_chassis="laptop"
+deviceinfo_keyboard="true"
+deviceinfo_external_storage="true"
+deviceinfo_screen_width="1920"
+deviceinfo_screen_height="1080"
+
+# Bootloader related
+deviceinfo_flash_method="none"
+deviceinfo_boot_filesystem="fat32"
+deviceinfo_generate_systemd_boot="true"
+deviceinfo_dtb="qcom/sdm850-lenovo-yoga-c630"
+deviceinfo_kernel_cmdline="console=ttyMSM0,115200 console=tty0 clk_ignore_unused pd_ignore_unused arm64.nopauth"
+deviceinfo_getty="ttyMSM0;115200"
+
@@ -0,0 +1,25 @@
+jbd2
+mbcache
+scsi_mod
+sd_mod
+sg
+libata
+sd
+ahci
+libahci
+hid-generic
+hid-multitouch
+i2c-qcom-geni
+i2c-hid
+i2c-hid-of
+usb_storage
+usb
+xhci_hcd
+ehci_hcd
+msm
+display-connector
+ti-sn65dsi86
+panel-edp
+phy-qcom-edp
+pwm_bl
+
@@ -2,7 +2,7 @@
 # Reference: <https://postmarketos.org/devicepkg>
 pkgname=device-postmarketos-trailblazer
 pkgdesc="postmarketOS Trailblazer generic ARM64"
-pkgver=4
+pkgver=6
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -21,6 +21,7 @@ depends="
 	systemd-boot
 	firmware-siliconlabs-rs9116
 	firmware-brcm43752
+	dtbloader
 "
 makedepends="devicepkg-dev"
 source="
@@ -37,6 +38,6 @@ package() {
 }

 sha512sums="
-1f353c9ccca43a43bf04b115f87d07ff472b19ca41ac2289d69f2453c708b12f4d5421599c752ed4ed75455ea341dd3f3c6766117282786933e878a109777fef  deviceinfo
+255f7477ad35723cdfdac91969d3facd4879cb858dbcaf990abe11a0ff2e975941ba98e5e10dd243765f15539c9aee18242cd31b9438008846867c703e98c421  deviceinfo
 71fa3c8b3e7b001be910a64650213854b31db667286f59566bcd27db496f37ad43905d8526d8e061057d04d7e21a36da185eac845a4d7826969ecdf0cabc3f85  modules-initfs
 "
@@ -23,5 +23,3 @@ deviceinfo_partition_type="gpt"
 deviceinfo_boot_filesystem="fat32"
 deviceinfo_generate_systemd_boot="true"

-# Required for devices using UFS as storage (instead of e.g. eMMC)
-deviceinfo_rootfs_image_sector_size="4096"
@@ -0,0 +1,38 @@
+# Reference: <https://postmarketos.org/devicepkg>
+pkgname=device-xiaomi-jasmine_sprout
+pkgdesc="Xiaomi Mi A2"
+pkgver=1
+pkgrel=0
+url="https://postmarketos.org"
+license="MIT"
+arch="aarch64"
+options="!check !archcheck"
+depends="
+	firmware-xiaomi-jasmine_sprout
+	firmware-qcom-adreno-a530
+	linux-postmarketos-qcom-sdm660
+	mkbootimg
+	msm-firmware-loader
+	postmarketos-base
+	soc-qcom-sdm660
+	soc-qcom-sdm660-rproc
+
+"
+makedepends="devicepkg-dev"
+source="
+	deviceinfo
+	modules-initfs
+"
+
+build() {
+	devicepkg_build $startdir $pkgname
+}
+
+package() {
+	devicepkg_package $startdir $pkgname
+}
+
+sha512sums="
+2e435e92d30e4e1b8a8aa8be6ba17dd3704669f134ccb8a44fd2456fc1ef2a9f78edab0b1a441352bbb8fda6e6cb5d5ad0c9592f1e1ee896bdc36a76a5e2b491  deviceinfo
+0900c2f930d1c3f2a6a2b9b8b35ecfe54a1d3aa1932f9dbea55a85c68c502f59c8d1a0196f15834ffd16d31bc073247c7c841279efb8aed81af2487f89442963  modules-initfs
+"
@@ -0,0 +1,33 @@
+# Reference: <https://postmarketos.org/deviceinfo>
+# Please use double quotes only. You can source this file in shell scripts.
+
+deviceinfo_format_version="0"
+deviceinfo_name="Xiaomi Mi A2"
+deviceinfo_manufacturer="Xiaomi"
+deviceinfo_codename="xiaomi-jasmine_sprout"
+deviceinfo_year="2018"
+deviceinfo_dtb="qcom/sdm660-xiaomi-jasmine"
+deviceinfo_append_dtb="true"
+deviceinfo_arch="aarch64"
+deviceinfo_flash_kernel_on_update="true"
+
+# Device related
+deviceinfo_gpu_accelerated="true"
+deviceinfo_chassis="handset"
+deviceinfo_keyboard="false"
+deviceinfo_external_storage="false"
+deviceinfo_screen_width="1080"
+deviceinfo_screen_height="2160"
+
+# Bootloader related
+deviceinfo_flash_method="fastboot"
+deviceinfo_flash_fastboot_partition_vbmeta="vbmeta"
+deviceinfo_generate_bootimg="true"
+deviceinfo_bootimg_qcdt="false"
+deviceinfo_bootimg_dtb_second="false"
+deviceinfo_flash_pagesize="4096"
+deviceinfo_flash_offset_base="0x00000000"
+deviceinfo_flash_offset_kernel="0x00008000"
+deviceinfo_flash_offset_ramdisk="0x01000000"
+deviceinfo_flash_offset_second="0x00f00000"
+deviceinfo_flash_offset_tags="0x00000100"
@@ -0,0 +1,2 @@
+msm
+panel-novatek-nt36672-tianma-jasmine
@@ -0,0 +1,29 @@
+# Maintainer: Caleb Connolly <caleb@connolly.tech>
+
+pkgname=firmware-lenovo-yoga-c630
+pkgver=1
+pkgrel=0
+pkgdesc="Firmware for Lenovo Yoga C630"
+url="https://gitlab.com/sdm845-mainline/firmware-lenovo-yoga-c630"
+arch="aarch64"
+depends="linux-firmware-qcom linux-firmware-ath10k"
+license="proprietary"
+options="!check !strip !archcheck !tracedeps pmb:cross-native"
+
+_commit="6ddfd13d1bb0dcaf56dd0ffe9387f745a08eb80f"
+
+source="$pkgname-$_commit.tar.gz::https://gitlab.com/sdm845-mainline/firmware-lenovo-yoga-c630/-/archive/$_commit/$pkgname-$_commit.tar.gz
+	firmware.files"
+builddir="$srcdir/$pkgname-$_commit"
+
+package() {
+	cd "$builddir"
+	for file in $(cat "$srcdir/firmware.files"); do
+		install -Dm644 "$file" "$pkgdir/$file"
+	done
+}
+
+sha512sums="
+c04d565c05c794c2da96cfbccb4ab9d4b406b8da34924901ab49002f6161c2c51e4cfc818f9cb0701ee0e7f4646280e4cc2fb441da3a0ff2514f5264934c2941  firmware-lenovo-yoga-c630-6ddfd13d1bb0dcaf56dd0ffe9387f745a08eb80f.tar.gz
+5b3d312ad96868893ed1faad822d66ecc723f5d803b0a94a42db7d53d228a4d86cc80c873e1a62bdca0c4ca371473703157ccbe1832abe28af90e5b3d1ec815f  firmware.files
+"
@@ -0,0 +1,18 @@
+./lib/firmware/postmarketos/qca/crbtfw21.tlv
+./lib/firmware/postmarketos/qca/crnv21.bin
+./lib/firmware/postmarketos/ipa_fws.mdt
+./lib/firmware/qcom/sdm850/LENOVO/81JL/adspr.jsn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/adspua.jsn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/cdspr.jsn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/modemuw.jsn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcadsp850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qccdsp850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcdsp1v2850_nm.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcdsp2850_nm.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcslpi850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcslpi850_cls.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/qcvss850.mbn
+./lib/firmware/qcom/sdm850/LENOVO/81JL/wlanmdsp.mbn
@@ -0,0 +1,36 @@
+pkgname=firmware-xiaomi-jasmine_sprout
+pkgver=1
+pkgrel=0
+pkgdesc="Firmware files for Xiaomi Mi A2"
+url="https://gitlab.com/m.01001101.01010110/$pkgname"
+arch="aarch64"
+license="proprietary"
+options="!strip !check !archcheck !spdx !tracedeps pmb:cross-native"
+makedepends="qca-swiss-army-knife"
+
+_commit="b23003b2a8fa8f71374c72d69cfdbfd048e63c33"
+_muppets_commit="c7757f14a4eea2276d3ee6f6055621deff0ed32e"
+
+source="
+	$pkgname-$_commit.tar.gz::$url/-/archive/$_commit/$pkgname-$_commit.tar.gz
+	$pkgname-$_muppets_commit.tar.gz::https://github.com/TheMuppets/proprietary_vendor_xiaomi_wayne-common/archive/$_muppets_commit.tar.gz
+"
+
+builddir="src"
+_fwdir="/lib/firmware"
+
+package() {
+	ath10k-fwencoder --create \
+		--features=wowlan,no-nwifi-decap-4addr-padding,allows-mesh-bcast,mgmt-tx-by-ref,non-bmi,single-chan-info-per-channel  \
+		--set-wmi-op-version=tlv --set-htt-op-version=tlv \
+		--set-fw-api=5
+	install -Dm644 firmware-5.bin -t "$pkgdir/$_fwdir/ath10k/WCN3990/hw1.0/"
+	install -Dm644 $pkgname-$_commit/board-2.bin -t "$pkgdir/$_fwdir/ath10k/WCN3990/hw1.0/"
+	install -Dm644 proprietary_vendor_xiaomi_wayne-common-$_muppets_commit/proprietary/vendor/firmware/a512_zap.elf "$pkgdir/$_fwdir/postmarketos/a512_zap.mbn"
+}
+
+
+sha512sums="
+02ec26bae153c1bdcc4194bfb80aad1dd24fa8e82b7b0a3d59d5cf6389a81e0415f7394176291b3005ea4542f3793b314fb492d7263292311a431049f5e6ae6c  firmware-xiaomi-jasmine_sprout-b23003b2a8fa8f71374c72d69cfdbfd048e63c33.tar.gz
+012dca09032ed9a06b51b93769d5ed0c15146adc68ee8dc09a84958064314adbb621413494e399c0f8be443f939db22deaaca94fb29cfa7ad9223aa7745d77f7  firmware-xiaomi-jasmine_sprout-c7757f14a4eea2276d3ee6f6055621deff0ed32e.tar.gz
+"
@@ -0,0 +1,74 @@
+# Reference: <https://postmarketos.org/vendorkernel>
+# Kernel config based on: arch/arm/configs/android_tate_defconfig
+
+pkgname=linux-amazon-tate
+pkgver=3.0.72
+pkgrel=0
+pkgdesc="Amazon Kindle Fire HD (2nd Generation) kernel fork"
+arch="armv7"
+_carch="arm"
+_flavor="amazon-tate"
+url="https://kernel.org"
+license="GPL-2.0-only"
+options="!strip !check !tracedeps pmb:cross-native"
+makedepends="bash bc bison devicepkg-dev flex openssl-dev perl xz gcc6"
+
+# Compiler: GCC 6 (doesn't boot when compiled with newer versions)
+if [ "${CC:0:5}" != "gcc6-" ]; then
+	CC="gcc6-$CC"
+	HOSTCC="gcc6-gcc"
+	CROSS_COMPILE="gcc6-$CROSS_COMPILE"
+fi
+
+# Source
+_repository="android_kernel_amazon_bowser-common"
+_commit="1364d678a9f79abb6ab9310669700e6fabb51a24"
+_config="config-$_flavor.$arch"
+source="
+	$pkgname-$_commit.tar.gz::https://github.com/LineageOS/$_repository/archive/$_commit.tar.gz
+	$_config
+	gcc10-extern_YYLOC_global_declaration.patch
+	kernel-use-the-gnu89-standard-explicitly.patch
+	linux3.0-fix-piggy.lzma.S.patch
+	linux3.0-fix-piggy.lzo.S.patch
+	tate-fix-sun-solaris-style-flag-on-section.patch
+	revert_sysfs_readdir_lseek_race_fix.patch
+	ifdef-audio-dep-hdmi.patch
+"
+builddir="$srcdir/$_repository-$_commit"
+_outdir="out"
+
+prepare() {
+	default_prepare
+	. downstreamkernel_prepare
+}
+
+build() {
+	unset LDFLAGS
+	make O="$_outdir" ARCH="$_carch" CC="${CC:-gcc}" \
+		CFLAGS_MODULE=-fno-pic \
+		KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-postmarketOS"
+}
+
+package() {
+	downstreamkernel_package "$builddir" "$pkgdir" "$_carch" "$_flavor" "$_outdir"
+
+	make modules_install \
+		O="$_outdir" ARCH="$_carch" \
+		CC="${CC:-gcc}" \
+		KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-postmarketOS" \
+		INSTALL_MOD_STRIP=1 \
+		INSTALL_MOD_PATH="$pkgdir"
+}
+
+sha512sums="
+4a50a9beb3238adaf19b222e66216ce4ddee930d21f8d80ad43bcd557a7ba169687d3cb61479a7d2e79f898c9416a4fe520e0d681f46bb4370956c16cc36a47c  linux-amazon-tate-1364d678a9f79abb6ab9310669700e6fabb51a24.tar.gz
+f5fb6d2f80b635f813151c03014e628467a3f17e5958043155d270078d2146a28b6c055bf8f61d28d04e37857d8219c9e8381145320c65240e8ae67126d374fa  config-amazon-tate.armv7
+2b48f1bf0e3f70703d2cdafc47d5e615cc7c56c70bec56b2e3297d3fa4a7a1321d649a8679614553dde8fe52ff1051dae38d5990e3744c9ca986d92187dcdbeb  gcc10-extern_YYLOC_global_declaration.patch
+ad0182a483791fc88e058838bc331b2f04a75ba291e763767babdb815efadfc3b4fda97e69e2e3f00a426cabea088e35297a92bd287592597d1e309be68ee92c  kernel-use-the-gnu89-standard-explicitly.patch
+3c098328e45db14cbeff6a515bb373129e0d0983884178f413c5a4206704b356ddecdf58557a04b828b391dbfef3cea0e98b47834aa97b86496aa2fce0013b92  linux3.0-fix-piggy.lzma.S.patch
+8837c884060d87232ba3fa9fce0e815d7ddf33c82ad49260426fe83754baa2f4d92a36a17561083ac8b3674564b7433b3141cacc63b520deec52bbcc1d92d5c9  linux3.0-fix-piggy.lzo.S.patch
+2027d4a68d9537b9d487572c8de6a68e9608087156b4fbc185cd6bd9df2dd4147d9f0e517fd50e653c4d73584df3977d739561446ee00c9409015ffa138f732b  tate-fix-sun-solaris-style-flag-on-section.patch
+03a694cf3a6659afc6439df3cfff3c37b6bdcce05cd6286b97c8fc1892a8c3985bfce64e574a23ba79de8bd614f4b5b57fb9dd18b8640ef8786f533e5c88530d  revert_sysfs_readdir_lseek_race_fix.patch
+d4e6b179e3fc875c4aa5ac204c3cb9d14c85fa66b0d5ded55a10ab3f342f953083635a575fbc5092b66e5994a037b670b68cdb5217356db10eae587d306738aa  ifdef-audio-dep-hdmi.patch
+"
@@ -0,0 +1 @@
+../../.shared-patches/linux/gcc10-extern_YYLOC_global_declaration.patch
@@ -0,0 +1,36 @@
+Ifdef a few HDMI audio function calls behind the relevant SoC HDMI audio flag.
+Temporarily needed to avoid kernel hangs caused by interacting with audio.
+diff --git a/drivers/video/omap2/dss/hdmi_panel.c b/drivers/video/omap2/dss/hdmi_panel.c
+index 8503459e83c..696629debde 100644
+--- a/drivers/video/omap2/dss/hdmi_panel.c
+++ b/drivers/video/omap2/dss/hdmi_panel.c
+@@ -42,7 +42,9 @@ static ssize_t hdmi_audio_max_channel_show(struct device *dev,
+ 		struct device_attribute *attr, char *buf)
+ {
+ 	int r;
+#ifdef CONFIG_SND_OMAP_SOC_OMAP4_HDMI
+ 	r = hdmi_audio_get_max_channels();
+#endif
+ 	return snprintf(buf, PAGE_SIZE, "%d\n", r);
+ }
+ 
+@@ -335,7 +337,9 @@ static void hdmi_hotplug_detect_worker(struct work_struct *work)
+ 			mutex_unlock(&hdmi.hdmi_lock);
+ 			dssdev->driver->disable(dssdev);
+ 			omapdss_hdmi_enable_s3d(false);
+#ifdef CONFIG_SND_OMAP_SOC_OMAP4_HDMI
+ 			hdmi_audio_update_edid_info();
+#endif
+ 			mutex_lock(&hdmi.hdmi_lock);
+ 		}
+ 		goto done;
+@@ -358,7 +362,9 @@ static void hdmi_hotplug_detect_worker(struct work_struct *work)
+ 					dssdev->panel.monspecs.max_x * 10000;
+ 			dssdev->panel.height_in_um =
+ 					dssdev->panel.monspecs.max_y * 10000;
+#ifdef CONFIG_SND_OMAP_SOC_OMAP4_HDMI
+ 			hdmi_audio_update_edid_info();
+#endif
+ 			hdmi_inform_hpd_to_cec(true);
+ 			switch_set_state(&hdmi.hpd_switch, 1);
+ 			goto done;
@@ -0,0 +1 @@
+../../.shared-patches/linux/kernel-use-the-gnu89-standard-explicitly.patch
@@ -0,0 +1 @@
+../../.shared-patches/linux/linux3.0-fix-piggy.lzma.S.patch
@@ -0,0 +1 @@
+../../.shared-patches/linux/linux3.0-fix-piggy.lzo.S.patch
@@ -0,0 +1,48 @@
+commit bb5489176fda28aff304b59e0405f7d7d4906224
+Author: Jiri Kosina <jkosina@suse.cz>
+Date:   Mon Apr 22 15:40:15 2013 +0200
+
+    Revert "sysfs: fix race between readdir and lseek"
+    
+    This reverts commit 991f76f837bf22c5bb07261cfd86525a0a96650c in Linus'
+    tree which is f366c8f271888f48e15cc7c0ab70f184c220c8a4 in
+    linux-stable.git
+    
+    It depends on ef3d0fd27e90f ("vfs: do (nearly) lockless generic_file_llseek")
+    which is available only in 3.2+.
+    
+    When applied on 3.0 codebase, it causes A-A deadlock, whenever anyone does
+    seek() on sysfs, as both generic_file_llseek() and sysfs_dir_llseek() obtain
+    i_mutex.
+    
+    Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+    Cc: Jiri Slaby <jslaby@suse.cz>
+    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+diff --git a/fs/sysfs/dir.c b/fs/sysfs/dir.c
+index 7cbc5856feea..3ab78b873376 100644
+--- a/fs/sysfs/dir.c
+++ b/fs/sysfs/dir.c
+@@ -959,21 +959,9 @@ static int sysfs_readdir(struct file * filp, void * dirent, filldir_t filldir)
+ 	return 0;
+ }
+ 
+-static loff_t sysfs_dir_llseek(struct file *file, loff_t offset, int whence)
+-{
+-	struct inode *inode = file->f_path.dentry->d_inode;
+-	loff_t ret;
+-
+-	mutex_lock(&inode->i_mutex);
+-	ret = generic_file_llseek(file, offset, whence);
+-	mutex_unlock(&inode->i_mutex);
+-
+-	return ret;
+-}
+-
+ const struct file_operations sysfs_dir_operations = {
+ 	.read		= generic_read_dir,
+ 	.readdir	= sysfs_readdir,
+ 	.release	= sysfs_dir_release,
+-	.llseek		= sysfs_dir_llseek,
+	.llseek		= generic_file_llseek,
+ };
@@ -0,0 +1,43 @@
+Replace Solaris-style section flags with GNU equivalent.
+
+The regular version in shared-patches doesn't apply cleanly to this kernel tree,
+so a separate patch is needed.
+diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S
+index 25ab26f1c6f..f22428e275f 100644
+--- a/arch/arm/boot/compressed/big-endian.S
+++ b/arch/arm/boot/compressed/big-endian.S
+@@ -5,7 +5,7 @@
+  *  Author: Nicolas Pitre
+  */
+ 
+-	.section ".start", #alloc, #execinstr
+	.section ".start", "ax"
+ 
+ 	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+ 	orr	r0, r0, #(1 << 7)	@ enable big endian mode
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index caddb9d35b7..3ba2ca1b202 100644
+--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
+@@ -112,7 +112,7 @@
+ #endif
+ 		.endm
+ 
+-		.section ".start", #alloc, #execinstr
+		.section ".start", "ax"
+ /*
+  * sort out different calling conventions
+  */
+diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
+index f649f1c589e..3ec865c11c9 100644
+--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
+@@ -477,7 +477,7 @@ cpu_elf_name:
+ 	.size	cpu_elf_name, . - cpu_elf_name
+ 	.align
+ 
+-	.section ".proc.info.init", #alloc, #execinstr
+	.section ".proc.info.init", "ax"
+ 
+ 	.type   __v7_ca9mp_proc_info, #object
+ __v7_ca9mp_proc_info:
@@ -0,0 +1,76 @@
+# Maintainer: Caleb Connolly <caleb@postmarketos.org>
+# Kernel config based on: arch/arm64/configs/defconfig
+
+pkgname=linux-next
+pkgver=6.11_git20240809
+pkgrel=1
+_nextver="${pkgver#*_git}"
+pkgdesc="Linux next kernel"
+arch="aarch64"
+_carch="arm64"
+_flavor="generic-trailblazer"
+url="https://kernel.org"
+license="GPL-2.0-only"
+# FIXME: kconfigcheck isn't supported since we use fragments
+options="!strip !check !tracedeps pmb:cross-native"
+source="
+	https://gitlab.com/linux-kernel/linux-next/-/archive/next-$_nextver/linux-next-next-$_nextver.tar.gz
+	devices.config
+	pmos.config
+"
+makedepends="
+	bash
+	bc
+	bison
+	devicepkg-dev
+	findutils
+	flex
+	git
+	linux-headers
+	openssl-dev
+	perl
+	python3
+	zstd
+"
+builddir="$srcdir/linux-next-next-$_nextver"
+
+prepare() {
+	default_prepare
+	cp "$srcdir/pmos.config" "$builddir"/arch/"$_carch"/configs/
+	cp "$srcdir/devices.config" "$builddir"/arch/"$_carch"/configs/
+
+	# Generate .config
+	unset LDFLAGS
+	make ARCH="$_carch" CC="${CC:-gcc}" \
+		KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-next-$_nextver" \
+		defconfig pmos.config devices.config
+}
+
+build() {
+	unset LDFLAGS
+	make O="$_outdir" ARCH="$_carch" CC="${CC:-gcc}" \
+		KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-postmarketOS"
+}
+
+package() {
+	install -Dm644 "$builddir/arch/$_carch/boot/vmlinuz.efi" \
+			"$pkgdir/boot/linux.efi"
+
+	make modules_install dtbs_install \
+		ARCH="$_carch" \
+		INSTALL_PATH="$pkgdir"/boot/ \
+		INSTALL_MOD_PATH="$pkgdir" \
+		INSTALL_MOD_STRIP=1 \
+		INSTALL_DTBS_PATH="$pkgdir"/boot/dtbs
+
+	rm -f "$pkgdir"/lib/modules/*/build "$pkgdir"/lib/modules/*/source
+
+	install -D "$builddir"/include/config/kernel.release \
+		"$pkgdir"/usr/share/kernel/next-"$_nextver"/kernel.release
+}
+
+sha512sums="
+9e298609e6e1739867ed6255891b6a0aadc06c6ba229c661e4a3afa637167750e6190146bc5c091f41ce1ebebeaf5e86809aa504c80c4d44789a8098db87ee48  linux-next-next-20240809.tar.gz
+adbb506c0a2d676b1964a5d7c693f72338541ebd0cacee62e4579d43163c468d95607d73bf7439fb55b4d6bfa0dd42578b07ee20965aa03c2a9d8022cb3ae267  devices.config
+d52f692935675b5b9300c7983848a26149914687a8b3aef3b90f50da3f6534de9b490c6778d490bb5a4202f1a45cc4d9178a1e1b8270a8d612d4181721629c02  pmos.config
+"
@@ -0,0 +1,39 @@
+# Config fragment for device features which aren't enabled in the upstream
+# defconfig. Use of =y heavily discouraged.
+
+# sdm845
+# Lenovo Yoga C630
+CONFIG_EC_LENOVO_YOGA_C630=m
+CONFIG_BATTERY_LENOVO_YOGA_C630=m
+CONFIG_UCSI_LENOVO_YOGA_C630=m
+# OnePlus 6/6T
+CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
+CONFIG_RMI4_CORE=m
+CONFIG_RMI4_I2C=m
+CONFIG_RMI4_F03_SERIO=m
+CONFIG_RMI4_2D_SENSOR=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F30=y
+# SHIFT6mq
+CONFIG_DRM_PANEL_VISIONOX_RM69299=m
+
+# sc7180
+CONFIG_SC_DISPCC_7180=m
+CONFIG_SC_GPUCC_7180=m
+CONFIG_SC_LPASS_CORECC_7180=m
+CONFIG_SC_VIDEOCC_7180=m
+# Acer Aspire 1
+CONFIG_EC_ACER_ASPIRE1=m
+
+# msm8916
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_EXTCON_QCOM_SPMI_MISC=m
+# gt58/gt510
+CONFIG_TOUCHSCREEN_ZINITIX=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0=m
+CONFIG_PWM_CLK=m
+CONFIG_SND_SOC_TFA989X=m
+CONFIG_CM3323=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+
@@ -0,0 +1,228 @@
+# general
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CGROUPS=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_DEVTMPFS=y
+CONFIG_DM_CRYPT=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_SYSVIPC=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_VT=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_CGROUP_BPF=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_USER_NS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_SAMSUNG_TUI=n
+CONFIG_TZDEV=n
+
+# filesystems
+CONFIG_BTRFS_FS=m
+CONFIG_EXFAT_FS=m
+CONFIG_EXT4_FS=m
+CONFIG_F2FS_FS=m
+CONFIG_NLS_ASCII=y
+
+# FDE
+CONFIG_MD=y
+CONFIG_CRYPTO_SHA256=y # TODO: make this module
+CONFIG_CRYPTO_AES=y # TODO: make this module
+
+# nftables
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NFT_CT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_REJECT=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_NAT=m
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_NAT=m
+
+# wireguard
+CONFIG_WIREGUARD=m
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_CT=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_CONNTRACK_MARK=y
+
+# waydroid
+CONFIG_ANDROID_BINDERFS=n
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDER_IPC_SELFTEST=n
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BPF_SYSCALL=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_CGROUP_BPF=y
+CONFIG_FUSE_FS=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_VLAN_8021Q=m # prerequisite for bridge
+
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_PSI=y
+CONFIG_PSI_DEFAULT_DISABLED=n
+
+# iwd
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_CRYPTO_AES=y # TODO: make this module
+CONFIG_CRYPTO_CBC=y # TODO: make this module
+CONFIG_CRYPTO_CMAC=y # TODO: make this module
+CONFIG_CRYPTO_DES=y # TODO: make this module
+CONFIG_CRYPTO_ECB=y # TODO: make this module
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD5=y # TODO: make this module
+CONFIG_CRYPTO_SHA1=y # TODO: make this module
+CONFIG_CRYPTO_SHA256=y # TODO: make this module
+CONFIG_CRYPTO_SHA512=y # TODO: make this module
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_KEYS=y
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_RFKILL=m
+
+# containers (lxc, Docker)
+CONFIG_NAMESPACES=y
+CONFIG_NET_NS=y
+CONFIG_PID_NS=y
+CONFIG_IPC_NS=y
+CONFIG_UTS_NS=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CPUSETS=y
+CONFIG_KEYS=y
+CONFIG_VETH=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m # needed for lxc
+CONFIG_IP_NF_NAT=m
+CONFIG_NF_NAT=m
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BLK_DEV_DM=m # Storage Drivers
+CONFIG_DUMMY=m # Network Drivers
+CONFIG_USER_NS=y
+CONFIG_BLK_CGROUP=y # Optional section
+CONFIG_BLK_DEV_THROTTLING=y # Optional section
+CONFIG_CGROUP_PERF=y # Optional section
+CONFIG_NET_CLS_CGROUP=m # Optional section
+CONFIG_NET_SCHED=y # Optional section
+CONFIG_FAIR_GROUP_SCHED=y # Optional section
+CONFIG_RT_GROUP_SCHED=y # Optional section
+CONFIG_IP_NF_TARGET_REDIRECT=m # Optional section
+CONFIG_IP_VS=m # Optional section
+CONFIG_IP_VS_NFCT=y # Optional section
+CONFIG_IP_VS_PROTO_TCP=y # Optional section
+CONFIG_IP_VS_PROTO_UDP=y # Optional section
+CONFIG_IP_VS_RR=m # Optional section
+CONFIG_EXT4_FS=m
+CONFIG_EXT4_FS_POSIX_ACL=y # Optional section
+CONFIG_EXT4_FS_SECURITY=y # Optional section
+CONFIG_CFS_BANDWIDTH=y # Optional section
+CONFIG_CHECKPOINT_RESTORE=y # Needed for lxc
+CONFIG_MEMCG=y
+CONFIG_DM_THIN_PROVISIONING=m # Storage Drivers
+CONFIG_SWAP=y
+CONFIG_VXLAN=m # Network Drivers
+CONFIG_IP6_NF_TARGET_MASQUERADE=m # Needed for lxc
+CONFIG_BRIDGE_VLAN_FILTERING=y # This is already enabled
+CONFIG_MACVLAN=m # Network Drivers
+CONFIG_CGROUP_NET_PRIO=y # Optional section
+CONFIG_OVERLAY_FS=m # Storage Drivers
+CONFIG_IPVLAN=m # Network Drivers
+CONFIG_SECCOMP=y # Optional section
+CONFIG_CGROUP_PIDS=y # Optional section
+
+# zram
+CONFIG_ZRAM=m
+CONFIG_ZSMALLOC=m
+CONFIG_ZSMALLOC_STAT=y
+CONFIG_ZRAM_MEMORY_TRACKING=y
+CONFIG_CRYPTO_LZ4=m
+CONFIG_LZ4_COMPRESS=m
+CONFIG_SWAP=y
+
+# usb gadgets
+# disable legacy gadgets
+CONFIG_USB_ETH=n
+CONFIG_USB_FUNCTIONFS=n
+CONFIG_USB_MASS_STORAGE=n
+CONFIG_USB_G_SERIAL=n
+# enable configfs gadgets
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+
+# other
+CONFIG_BLK_DEV_NBD=y # netboot
+CONFIG_INPUT_UINPUT=m # fbkeyboard, buffyboard
+CONFIG_LEDS_TRIGGER_TIMER=m # hfd-service
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m # change MTU, e.g. for Wireguard
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m # change MTU, e.g. for Wireguard
+
+# EFI
+CONFIG_EFI_STUB=y
+CONFIG_EFI=y
+CONFIG_DMI=y
+CONFIG_EFI_ESRT=y
+CONFIG_PSTORE=y # dependency of CONFIG_EFI_VARS_PSTORE
+CONFIG_EFI_VARS_PSTORE=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+
+CONFIG_EFI_ZBOOT=y
+
+# Compress modules
+CONFIG_HAVE_KERNEL_ZSTD=y
+# Doesn't seem to be working correctly
+#CONFIG_MODULE_COMPRESS_ZSTD=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_DECOMPRESS_ZSTD=y
+
+# Enable dynamic debug
+CONFIG_DYNAMIC_DEBUG=y
@@ -3,8 +3,8 @@

 _flavor="postmarketos-qcom-sdm660"
 pkgname=linux-$_flavor
-pkgver=6.9.3
-pkgrel=1
+pkgver=6.9.9
+pkgrel=0
 pkgdesc="Close to mainline linux kernel for Qualcomm Snapdragon 660 SoC"
 arch="aarch64"
 url="https://kernel.org/"
@@ -63,6 +63,6 @@ package() {
 }

 sha512sums="
-ebe70e1364efa99f70e4a3725c42ea94e1c3834ffdec416a5eac8081c02489768d52525dfedaa0f65524d8082b910e647efae30d0795ea683284fcb20d532016  linux-v6.9.3-sdm660.tar.gz
+08116930f88e79bd3fc9b2625ca534d1271d74731868a779f4ea5bd826598bba72f1400d5589ad1a496110589a8d0bc4568dd5a4643d4db3627cf3c29c85334b  linux-v6.9.9-sdm660.tar.gz
 ff2dcdf202846376c8b2c1daf2caab6239582ddf947050043d3d32ff1cff71395af6c487c6c05534fda7f8a293d92884890565bcd6830a1db52b26bae1412c8d  config-postmarketos-qcom-sdm660.aarch64
 "
@@ -3,7 +3,7 @@

 pkgname=linux-samsung-a6lte
 pkgver=3.18.140
-pkgrel=5
+pkgrel=6
 pkgdesc="Samsung Galaxy A6 2018 kernel fork"
 arch="aarch64"
 _carch="arm64"
@@ -43,6 +43,7 @@ source="
 	disable-boot-mode-check.patch
 	uncomment-rfcomm-in-makefile.patch
 	linux3.7to4.5-ARM64-remove-Sun-Solaris-style-flag-on-section.patch
+	fix-addrconf_rt_table-nullptr-deref.patch
 "
 builddir="$srcdir/$_repository-$_commit"
 _outdir="."
@@ -74,7 +75,7 @@ package() {

 sha512sums="
 c2cc5190c480de4ac2d376827c5c56a542c6644d3dbeb47956d0b90c5570b246872ecedbf5655ac5564c9f61190d23567a4c496bb4235c46f6bd7a6d8addcc68  linux-samsung-a6lte-981969320c1cdc214cf8a1a357fab642f401a5d1.tar.gz
-bac785d34c8e5e986c2a17cc5cc0a975d4d87ef5b01a6496cc89cac274f28a33b76a514515f0819e6b6ca2337ee19b7eb0e3c86f88bea93abea69a9de98658ee  config-samsung-a6lte.aarch64
+82ca91133a27967d164c5e38545bfe84055c0ec7dde738038ba8258a05d518e07b16a2ba7b9c1b7dda28236dbdc62def3cfb643ae695bca88498714b6fd25e56  config-samsung-a6lte.aarch64
 2b48f1bf0e3f70703d2cdafc47d5e615cc7c56c70bec56b2e3297d3fa4a7a1321d649a8679614553dde8fe52ff1051dae38d5990e3744c9ca986d92187dcdbeb  gcc10-extern_YYLOC_global_declaration.patch
 3f65a690e48f913fcb980718fae4dc03c29a6dc86eecb1e2af644488ad415de326a61d840399fb69915cbc5d56d5586f2df2287b3e7323a2927ae73a3b1b1373  zram-zs-create-pool-null.patch
 5bd204239a5daff9f990757178398707ae5ec64f823ed9ec72a8d50ebe6d5f0a3cc9743e0d775094da4b3a7566f1ccceb56f39f3b0234d08ca05e537d86271ec  decon-fb-colors.patch
@@ -82,4 +83,5 @@ e1409844c46869ffe6ac9e028c3f38868120b6fd38dcf52ca7c1fdb98e90d2717d72ed52f7f41d3b
 1e705ff6f256b93986adba4c1f296b2d47be48986490d6a1130fc57126a462b2adfb4f51d3717ef70e91d0b42eb54a33b0d29f85d0c0bb9bf1498bb80c1bb7c1  disable-boot-mode-check.patch
 cd41a79406341cb72b4d569b21b2af3bbba4fcedd891a73b3273d5e9561466d5b99c424ce29bac83650298fc51d53b5cb65037a644f622a7e287ec38d30af66f  uncomment-rfcomm-in-makefile.patch
 75545ccd0082a119b9ad95fcef3523c939a5c946f8f3a5c3dde15cee1502f6c1011050a0ad5359426f018bb7ceea1c97a28c7665941bc89f365c8d11065ce0f6  linux3.7to4.5-ARM64-remove-Sun-Solaris-style-flag-on-section.patch
+713bfcbcd6c78d554fc1e50746792b25dfde455c98cef483ad9b07044171fd064d266ffbc9338bb1aa42d921f583433b00f4586cf8b03c6d21468ca88bd60fed  fix-addrconf_rt_table-nullptr-deref.patch
 "
@@ -4577,7 +4577,7 @@ CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
-CONFIG_CRYPTO_FIPS=y
+# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
@@ -0,0 +1,12 @@
+--- a/net/ipv6/addrconf.c	2022-02-08 08:17:30.000000000 +0300
+++ b/net/ipv6/addrconf.c	2024-08-06 00:58:50.314960285 +0300
+@@ -2125,6 +2125,9 @@
+ 	 * - If < 0, put routes into table dev->ifindex + (-rt_table).
+ 	 */
+ 	struct inet6_dev *idev = in6_dev_get(dev);
+	if (!idev) {
+		return 0;
+	}
+ 	u32 table;
+ 	int sysctl = idev->cnf.accept_ra_rt_table;
+ 	if (sysctl == 0) {
@@ -1,6 +1,6 @@
 # Maintainer: Clayton Craft <clayton@craftyguy.net>
 pkgname=boot-deploy
-pkgver=0.17
+pkgver=0.18
 pkgrel=0
 pkgdesc="tool for finalizing and deploying boot related files"
 url="https://gitlab.com/postmarketos/boot-deploy"
@@ -28,5 +28,5 @@ package() {
 }
 sha512sums="
 a243975b9850d9933e0f917f7eb38fc4a76ea658c3dcc56f035f60ee6c62d6740c1107143b8210bdc0231d4c9b6b2003e458120985604eb09649322d359ae89f  os-customization
-db77ffa700087d60d3ff0a8708c4ca68234eaa019ff7ea5f2c2c4035c77c20b325bd9ce22d155213d2b38766ff31fd82ca51b8f66067b6dda072a425b978162c  boot-deploy-0.17.tar.gz
+e4b059c149a96f896804c7971107f738852bf1dfadd5832e4e2b3ebf2bf00f05570bd45f0f2bea69f54755fbf6bffc9091a1d6baed7b1537679afef5c44a5fd0  boot-deploy-0.18.tar.gz
 "
@@ -0,0 +1,41 @@
+# Contributor: Nikita Travkin <nikita@trvn.ru>
+# Maintainer: Nikita Travkin <nikita@trvn.ru>
+pkgname=dtbloader
+pkgver=1.1
+pkgrel=0
+pkgdesc="EFI driver that finds and installs DeviceTree into the UEFI configuration table"
+url="https://github.com/TravMurav/dtbloader"
+arch="aarch64"
+license="BSD-3-Clause"
+makedepends="clang cmd:llvm-ar lld"
+options="!check"
+subpackages="$pkgname-boot-deploy:boot_deploy"
+source="https://github.com/TravMurav/dtbloader/releases/download/$pkgver/dtbloader-$pkgver.tar.gz"
+builddir="$srcdir"
+
+build() {
+	make \
+		ABORT_IF_UNSUPPORTED=1 \
+		O=build
+
+	./scripts/get_supported_dtbs.sh > "$builddir"/build/dtbs.txt
+}
+
+package() {
+	install -Dt "$pkgdir"/usr/share/dtbloader \
+		"$builddir"/build/dtbloader.efi \
+		"$builddir"/build/dtbs.txt
+}
+
+boot_deploy() {
+	pkgdesc="boot-deploy integration for dtbloader"
+	install_if="$pkgname=$pkgver-r$pkgrel boot-deploy"
+
+	mkdir -p "$subpkgdir"/usr/share/boot-deploy/efi-drivers/
+	ln -s /usr/share/dtbloader/dtbloader.efi \
+		"$subpkgdir"/usr/share/boot-deploy/efi-drivers/dtbloaderaa64.efi
+}
+
+sha512sums="
+7fe2c4bac469afdcb665d3026ebfa2d539a6c6c043bf0bd923d95446455969241cb57617a7a46052ab5dfee76c264050b5c57c2da57691c32f97d8aedb0071cc  dtbloader-1.1.tar.gz
+"
@@ -1,7 +1,7 @@
 # Maintainer: Oliver Smith <ollieparanoid@postmarketos.org>
 pkgname=postmarketos-base-ui-gnome
 pkgver=3
-pkgrel=9
+pkgrel=10
 pkgdesc="Meta package for shared configuration for GNOME-based UIs"
 url="https://postmarketos.org"
 arch="noarch"
@@ -62,6 +62,7 @@ openrc() {
 		elogind-openrc
 		iio-sensor-proxy-openrc
 		modemmanager-openrc
+		networkmanager-openrc
 		polkit-elogind
 	"

@@ -2,7 +2,7 @@
 # Maintainer: Bart Ribbers <bribbers@disroot.org>
 pkgname=postmarketos-base-ui-plasma
 pkgver=2
-pkgrel=5
+pkgrel=7
 pkgdesc="Meta package for shared configuration for Plasma-based UIs"
 url="https://postmarketos.org"
 arch="noarch !armhf" # armhf is not supported
@@ -31,7 +31,6 @@ _pmb_recommends="
 	breeze-gtk
 	discover
 	flatpak
-	font-droid-nonlatin
 	font-noto
 	font-noto-emoji
 	font-noto-extra
@@ -74,6 +73,7 @@ openrc() {
 		elogind
 		elogind-openrc
 		iio-sensor-proxy-openrc
+		networkmanager-openrc
 		urfkill-openrc
 		"

@@ -1,6 +1,6 @@
 # Maintainer: Clayton Craft <clayton@craftyguy.net>
 pkgname=postmarketos-base-ui
-pkgver=26
+pkgver=27
 pkgrel=0
 pkgdesc="Meta package for minimal postmarketOS UI base"
 url="https://postmarketos.org"
@@ -12,6 +12,7 @@ depends="
 	font-dejavu
 	haveged
 	nftables
+	openssh-server-pam
 	pipewire
 	postmarketos-artwork-icons
 	postmarketos-base
@@ -70,6 +71,7 @@ _source644="
 	usr/share/wireplumber/wireplumber.conf.d/50-bluetooth.conf
 "
 _source600="
+	etc/ssh/sshd_config.d/postmarketos-ui-policy.conf
 	usr/lib/NetworkManager/system-connections/USB_Networking.nmconnection
 "
 _source755="
@@ -315,6 +317,7 @@ d4b4c4fed2dee7266f6a87ae266691377593014943e2953e4cd87a59f3110f25bfb5f3f866cc8435
 6507eb31cdd694a7db0280246433118a650bf5d99fbe639f967ae2d95945429a7e03ca6feb5bb6e7b9fb14fcec21e13e51209a79edd0041e77b5bf76b129ed6f  rootfs-usr-lib-NetworkManager-conf.d-50-tethering.conf
 900554534191fa0797064d35350934cdd8af59f30f0ae7d8ec63c2e11c44a16c643d3024b6543940488cd590fec1d392548bcaacc3be88cddff90f69b17ece07  rootfs-usr-lib-NetworkManager-conf.d-50-use-dnsmasq.conf
 92930f027626825b027f585a9be180f8a6ebae6dc44d2cf8f9d43cce00db8cbb43c33fc341fe382abacb832ea1b6414dc4c8129d265b0258d096599b2e206a93  rootfs-usr-share-wireplumber-wireplumber.conf.d-50-bluetooth.conf
+ee59e9fd55a8458fa1f149890680c9353def9d49a52199d104f84db3fc588edf23e2acbb9fcf84c8bb4fd0bd8fe3186eb2cc444a3a7eeececcd8eee0d74037d9  rootfs-etc-ssh-sshd_config.d-postmarketos-ui-policy.conf
 1b8add60574ec4644197cb93263c0653325c2e88e03673de918be5fb3280c7b81e8e97dce498850a07f2f3307771c44f3c876922e5cbd5207523ede31816296f  rootfs-usr-lib-NetworkManager-system-connections-USB_Networking.nmconnection
 d1ddd43489e6016e3ffd716027ed2bae4a2ab5f213118bdbcb96750e267ab7c0367cd0e0e386300aa5550352653144f5caeddd790621fe0879f83ca1995bb65c  rootfs-etc-tinydm.d-env-wayland.d-50-firefox-wayland.sh
 ecaa57d033a119a53a6574c27636b7c89d659d75ea48a973a6a4ff6f90e5d07202529fd489bfc9dfc7430f5b60f40612f6d5c06f7fab47e681b0a3112a874058  rootfs-etc-tinydm.d-env-wayland.d-50-sdl-wayland.sh
@@ -0,0 +1 @@
+UsePAM yes
@@ -2,7 +2,7 @@
 # Maintainer: Oliver Smith <ollieparanoid@postmarketos.org>
 pkgname=postmarketos-ui-sway
 pkgver=3.1
-pkgrel=5
+pkgrel=7
 pkgdesc="(Wayland) Tiling WM, drop-in replacement for i3wm (DOES NOT RUN WITHOUT HW ACCELERATION!)"
 url="https://postmarketos.org"
 arch="noarch"
@@ -54,6 +54,7 @@ openrc() {
 		bluez-openrc
 		elogind-openrc
 		modemmanager-openrc
+		networkmanager-openrc
 		seatd-openrc
 		tinydm-openrc
 		"
@@ -0,0 +1,58 @@
+# Forked from Alpine to test alternative sip backend
+
+pkgname=calls
+pkgver=46.3
+pkgrel=1
+pkgdesc="Phone dialer and call handler"
+arch="all"
+url="https://gitlab.gnome.org/GNOME/calls"
+license="GPL-3.0-or-later"
+depends="
+	callaudiod
+	modemmanager
+	"
+makedepends="
+	callaudiod-dev
+	evolution-data-server-dev
+	desktop-file-utils
+	feedbackd-dev
+	folks-dev
+	gettext-dev
+	gobject-introspection-dev
+	gom-dev
+	gsound-dev
+	gstreamer-dev
+	gtk+3.0-dev
+	libhandy1-dev
+	libpeas-dev
+	meson
+	modemmanager-dev
+	ninja
+	py3-docutils
+	sofia-sip-linphone-dev
+	vala
+	"
+subpackages="$pkgname-doc $pkgname-dbg $pkgname-lang"
+source="https://download.gnome.org/sources/calls/${pkgver%%.*}/calls-$pkgver.tar.xz
+	"
+options="!check" # Requires running Wayland compositor
+
+build() {
+	abuild-meson \
+		-Db_lto=true \
+		-Dtests="$(want_check && echo true || echo false)" \
+		. output
+	meson compile -C output
+}
+
+check() {
+	meson test --no-rebuild --print-errorlogs -C output
+}
+
+package() {
+	DESTDIR="$pkgdir" meson install --no-rebuild -C output
+}
+
+sha512sums="
+e128b6ddc6986ceb1335641f28a03111925e58a66de42276f25b5f4e030d4f448b193ca311502448c12876e0a2b3a84a1d6583480741ea13fc180aadef6f7314  calls-46.3.tar.xz
+"
@@ -2,7 +2,7 @@

 pkgname=mutter-mobile
 pkgver=46.0
-pkgrel=0
+pkgrel=1
 pkgdesc="clutter-based window manager and compositor"
 url="https://wiki.gnome.org/Projects/Mutter/"
 # ricsv64: doesn't build currently:
@@ -81,7 +81,6 @@ prepare() {

 build() {
 	abuild-meson \
-		-Degl_device=true \
 		-Dudev=true \
 		-Dnative_backend=true \
 		-Dintrospection=true \
@@ -0,0 +1,30 @@
+From 551ba7e1e0af3ae7a19a6bf6909db8178a2563cd Mon Sep 17 00:00:00 2001
+From: Stefan Hansson <newbyte@postmarketos.org>
+Date: Sat, 17 Aug 2024 20:27:40 +0200
+Subject: [PATCH] Remove bc suffix from version
+
+abuild doesn't like this. While it might seem appealing to strip this
+using some sed invocation to make this more futureproof, in practice
+this is a fool's errand as since this release they changed the build
+system from Autotools to CMake, so any future release will use CMake
+anyway which consequently makes any changes to configure.ac pointless.
+---
+ configure.ac | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configure.ac b/configure.ac
+index cbd57c4d..59fa82cc 100644
+--- a/configure.ac
+++ b/configure.ac
+@@ -11,7 +11,7 @@ dnl information on the package
+ dnl ---------------------------
+ 
+ dnl update both the version for AC_INIT and the LIBSOFIA_SIP_UA_MAJOR_MINOR
+-AC_INIT([sofia-sip], [1.13.45bc])
+AC_INIT([sofia-sip], [1.13.45])
+ AC_CONFIG_SRCDIR([libsofia-sip-ua/sip/sofia-sip/sip.h])
+ AC_CONFIG_MACRO_DIR([m4])
+ AC_SUBST(VER_LIBSOFIA_SIP_UA_MAJOR_MINOR, [1.13])
+-- 
+2.45.2
+
@@ -0,0 +1,44 @@
+# Contributor: Francesco Colista <fcolista@alpinelinux.org>
+# Maintainer: Francesco Colista <fcolista@alpinelinux.org>
+pkgname=sofia-sip-linphone
+pkgver=1.13.45
+_pkgver="${pkgver}bc"
+pkgrel=0
+pkgdesc="RFC3261 compliant SIP User-Agent library"
+url="https://gitlab.linphone.org/BC/public/external/sofia-sip"
+arch="all"
+license="LGPL-2.1-only"
+options="!check"
+makedepends="automake autoconf coreutils libtool m4 glib-dev openssl-dev>3 lksctp-tools-dev"
+subpackages="$pkgname-dev $pkgname-dbg $pkgname-doc"
+source="$pkgname-$_pkgver.tar.gz::https://github.com/BelledonneCommunications/sofia-sip/archive/$_pkgver.tar.gz
+	0001-Remove-bc-suffix-from-version.patch
+	"
+builddir="$srcdir/sofia-sip-$_pkgver"
+
+prepare() {
+	default_prepare
+	sh autogen.sh
+}
+
+build() {
+	./configure \
+		--prefix=/usr \
+		--with-openssl \
+		--enable-static=no \
+		--disable-rpath
+	make
+}
+
+check() {
+	TPORT_DEBUG=9 TPORT_TEST_HOST=0.0.0.0 make check
+}
+
+package() {
+	make DESTDIR="$pkgdir" install
+}
+
+sha512sums="
+4e6ed6c8ad0dba53c4c490abe248e8c537e00991d78e882ec93920477f6f2b36ee1fe5cfa90cea1c6f3d07fbccdd96adea881efd49e3aa89f647826ce8200344  sofia-sip-linphone-1.13.45bc.tar.gz
+f1dbeab1293f936092439d34046ae9fece6a283656746d92d49115c94a65c2a2061a55ff069949af663b8e96991c056cba5677efffce879eae2791ecf1b9263d  0001-Remove-bc-suffix-from-version.patch
+"
Author	SHA1	Message	Date
Stefan Hansson	9727972f51	temp/calls: fork to use sofia-sip-linphone [ci:skip-vercheck]	2024-08-17 21:12:56 +02:00
Stefan Hansson	d31ca07cc0	temp/sofia-sip-linphone: new aport	2024-08-17 21:09:38 +02:00
knuxify	6e172f9821	linux-postmarketos-exynos4: upgrade to 6.10.0 (MR 5477) - USB-OTG support for Midas boards (m0/t0) and Samsung Galaxy Tab 3 8.0 - Headset jack detection + headset mic support for Samsung Galaxy Tab 3 8.0 - Support for the Samsung Galaxy Note (q1) - Improved charging on Tab 3 8.0 and Midas boards - Minor improvements for Tab 3 8.0 (fix home keycode, enable fuel gauge current sensing) - Fixed #1783 The isorec initramfs is now stores in the exynos4-mainline linux repo and has been dropped from pmaports. [ci:skip-build]: already built successfully in CI	2024-08-17 16:45:05 +02:00
Blue Necko	d2dd5355d1	testing/device-asus-x00td: ath10k-wifi fix added extra dependencies (MR 5499)	2024-08-16 12:01:21 +09:00
Stefan Hansson	3f7be8037d	linux-purism-librem5: set CONFIG_LOGO=n (MR 5482) Otherwise we get penguins when the device first boots up. While I have nothing against Tux, this is a change that came as a result of the configuration being restarted to sync with Purism's configuration, and I think it visually clutters the boot sequence for no good reason. As such, disable this and return to the previous behaviour. [ci:skip-build]: already built successfully in CI	2024-08-15 13:43:29 -07:00
Caleb Connolly	183762f3ad	trailblazer: use default sector size (MR 5498) The 4k sector size is required for mobile, however we currently don't build a split image anyway (which is also necessary). Let's just go for 512 bytes so the prebuilt images can be flashed to a USB drive. [ci:skip-build]	2024-08-15 18:54:55 +02:00
Caleb Connolly	ceb1e1c6b2	CI: autoupdate: log build to stdout (MR 5498) Signed-off-by: Caleb Connolly <caleb@postmarketos.org>	2024-08-15 18:49:20 +02:00
Caleb Connolly	e065a3116a	CI: use large runner for autoupdate (MR 5498) Since we build linux-next before pushing to BPO, use the big runner so we don't delay the update by hours. BPO needs to build it again too... would be nice if we could push the artifact directly, ah well. Signed-off-by: Caleb Connolly <caleb@postmarketos.org>	2024-08-15 18:49:20 +02:00
Stefan Hansson	a46a9ac901	main/postmarketos-base-ui: set up PAM for ssh sessions (MR 5483) Seems to be enough to have $XDG_RUNTIME_DIR set for ssh sessions. Thanks to psykose for providing the necessary steps: https://gitlab.com/postmarketOS/pmaports/-/issues/2019#note_1408679900 Closes https://gitlab.com/postmarketOS/pmaports/-/issues/2019 [ci:skip-build]: already built successfully in CI	2024-08-15 09:08:27 -07:00
Nikita Travkin	e733418bb2	testing/linux-next: add few more configs (MR 5495) Add some extra configs needed for sc7180 as well as a couple of EC drivers for lapotps like aspire1 and c630	2024-08-15 23:44:14 +09:00
Robert Eckelmann	6161f370ab	main/postmarketos-ui-sway: fix typo in depends (MR 5497) Was looking by chance at the build status page and noticed images failing for sway. The cause is a typo introduced (missing "n") in the depends for `networkmanager-openrc` with `a22d0b0e03`. Signed-off-by: Robert Eckelmann <longnoserob@postmarketos.org> [ci:skip-build]: already built successfully in CI	2024-08-15 21:49:39 +09:00
Caleb Connolly	2ab7cbaf27	lenovo-yoga-c630: new device (MR 4726)	2024-08-15 21:31:17 +09:00
EliasOfWaffle	1b8c9af1c5	temp/mutter-mobile: remove EGL Device (MR 5304) EGL device is for eglstream backend from nvidia that is not necessary in mobile usage	2024-08-15 17:39:40 +09:00
WeirdTreeThing	2c32cc65fb	google-corsola: enable depthcharge image compression (MR 5376) Signed-off-by: Robert Eckelmann <longnoserob@postmarketos.org>	2024-08-15 17:26:43 +09:00
WeirdTreeThing	fe6558595a	google-cherry: enable depthcharge image compression (MR 5376)	2024-08-15 17:19:24 +09:00
WeirdTreeThing	82c5264d98	google-asurada: enable depthcharge image compression (MR 5376)	2024-08-15 17:19:24 +09:00
WeirdTreeThing	ce2ab7a168	google-trogdor: enable depthcharge image compression (MR 5376)	2024-08-15 17:19:19 +09:00
WeirdTreeThing	88ace37d67	google-oak: enable depthcharge image compression (MR 5376)	2024-08-15 17:19:18 +09:00
WeirdTreeThing	52338f9175	google-kukui: enable depthcharge image compression (MR 5376) Also switch back to the regular initramfs now that there is enough room for it.	2024-08-15 17:19:18 +09:00
WeirdTreeThing	f82b659498	google-gru: enable depthcharge image compression (MR 5376)	2024-08-15 17:19:18 +09:00
Sergey Lisov	36bf4eb5fe	linux-samsung-a6lte: fix nullptr dereference (MR 5467) I've had the kernel panic with a NULL pointer dereference in the addrconf_rt_table function. I have no idea how it could be triggered, but the fix is straightforward.	2024-08-15 10:03:42 +09:00
m.01001101.01010110	aaef79a7af	linux-postmarketos-qcom-sdm660: upgrade to 6.9.9 (MR 5485) This upgrade contains small fixes to jasmine_sprout's panel driver.	2024-08-14 01:46:58 +03:00
m.01001101.01010110	1319b6cfb8	xiaomi-jasmine_sprout: new device (Xiaomi Mi A2) (MR 5485)	2024-08-14 01:46:19 +03:00
Pablo Correa Gómez	0f3da7490d	main/postmarketos-base-ui-plasma: add networkmanager-openrc to depends (MR 5490) The service is enabled in the post-install script. This creates issues like https://gitlab.com/postmarketOS/pmaports/-/jobs/7550237979 [ci:skip-build]: already built successfully in CI	2024-08-13 10:05:33 +02:00
Pablo Correa Gómez	a22d0b0e03	main/postmarketos-ui-sway: add networkmanager-openrc to depends (MR 5490) The service is enabled in the post-install script. This creates issues like https://gitlab.com/postmarketOS/pmaports/-/jobs/7550237979	2024-08-13 10:05:32 +02:00
Pablo Correa Gómez	c5b6e46860	main/postmarketos-base-ui-gnome: add networkmanager-openrc to depends (MR 5490) The service is enabled in the post-install script. This creates issues like https://gitlab.com/postmarketOS/pmaports/-/jobs/7550237979	2024-08-13 10:05:32 +02:00
Oliver Smith	9ab02ada2c	CI: kconfig check: use --keep-going (MR 5491) Use the new --keep-going parameter so the check doesn't stop on first error. This was recently added in pmbootstrap MR 2384 to make the default behavior more userfriendly. [ci:skip-build]: already built successfully in CI	2024-08-13 10:02:43 +02:00
Connor Eliffe	ff89c7327e	amazon-tate: set pkgrel to 0 (MR 5473)	2024-08-11 19:38:18 +01:00
Connor Eliffe	c56b2644ab	linux-amazon-tate: fix APKBUILD indentation (MR 5473)	2024-08-11 19:38:18 +01:00
Connor Eliffe	ec55e7b98b	amazon-tate: new device (MR 5473)	2024-08-11 19:38:18 +01:00
Oliver Smith	315d85a71e	CI: autoupdate: build-test linux-next before push (MR 5481) Make sure that linux-next actually builds, before pushing the change to pmaports master. Otherwise it may block publishing other aarch64 packages in bpo.	2024-08-11 14:47:47 +02:00
Oliver Smith	729448922b	gitlab/issue_template: remove v23.12 (EOL)	2024-08-11 14:23:16 +02:00
Caleb Connolly	a7f6f00952	firmware-shift-sdm845: compressed mba.mbn wlanmdsp.mbn (MR 5480) These files from linux-firmware-qcom are compressed now, adjust the symlinks. Signed-off-by: Caleb Connolly <caleb@postmarketos.org> [ci:skip-build]: already built successfully in CI	2024-08-10 20:54:29 +02:00
knuxify	2b1a26bf25	cross/gcc-*: upgrade to 14.2.0-r1 (MR 5479) [ci:skip-build]	2024-08-10 23:30:06 +09:00
Nikita Travkin	00620d4c50	testing/device-postmarketos-trailblazer: Add dtbloader (MR 5458) Use dtbloader to pick the dtb on supported WoA devices. [ci:skip-vercheck]	2024-08-10 12:15:04 +09:00
Nikita Travkin	12be680839	main/dtbloader: New package (MR 5458) Add dtbloader efi driver to allow automatic dtb selection for generic images.	2024-08-10 12:13:55 +09:00
Øyvind Kolås	5c61e13964	device-google-corsola: fix symlink for zst compression (MR 5476)	2024-08-10 11:58:54 +09:00
postmarketOS CI	5233a4fc33	linux-next: upgrade to next-20240809	2024-08-09 18:31:56 +00:00
Masanori Ogino	2808d5283d	main/postmarketos-base-ui-plasma: remove font-droid-nonlatin (MR 5469) Other than Plasma-based UI, only Noto and Twemoji are installed by default. This change aligns Plasma with other UIs provided by pmOS. Resolves: https://gitlab.com/postmarketOS/pmaports/-/issues/3049	2024-08-09 12:15:11 +09:00
Clayton Craft	5eb4bda861	main/boot-deploy: upgrade to 0.18 (MR 5471) Features: - Add support for installing EFI drivers (MR 70) Fixes: - Fix dhtb header (MR 69) [ci:skip-build]: already built successfully in CI	2024-08-08 20:05:25 +02:00
Luca Weiss	fb029ff2d9	linux-next: add linux-headers make dependency (MR 5475) The host tool compiled from drivers/tty/vt/conmakehash.c requires linux/limits.h header which is not included (correctly?) inside the kernel source tree and is instead needed to be installed on the host. While this might not be totally correct, we need to get the package building to avoid blocking all aarch64 packages from getting published on our build system. Also while we're at it, sort the list of make dependencies. [ci:skip-vercheck]	2024-08-08 10:16:22 +02:00
				`@@ -0,0 +1 @@`
				`../../.shared-patches/linux/gcc10-extern_YYLOC_global_declaration.patch`
				`@@ -0,0 +1 @@`
				`../../.shared-patches/linux/kernel-use-the-gnu89-standard-explicitly.patch`
				`@@ -0,0 +1 @@`
				`../../.shared-patches/linux/linux3.0-fix-piggy.lzma.S.patch`