main/postmarketos-ui-lomiri: new aport

[ci:skip-build]: already built successfully in CI

.ci/autoupdate.sh

@@ -81,6 +81,9 @@ update_linux_next() {
 	# Update the checksums
 	pmbootstrap checksum linux-next
 
+	# Ensure it builds
+	pmbootstrap --details-to-stdout build linux-next
+
 	# Commit
 	git add device/testing/linux-next/APKBUILD
 	git commit -S -m "linux-next: upgrade to $latest"

.ci/lib/check_changed_kernels.py

@@ -17,7 +17,7 @@ def check_kconfig(pkgnames):
         pkgname = pkgnames[i]
         print(f"  ({i+1}/{len(pkgnames)}) {pkgname}")
 
-        p = subprocess.run(["pmbootstrap", "kconfig", "check", pkgname],
+        p = subprocess.run(["pmbootstrap", "kconfig", "check", "--keep-going", pkgname],
                            check=False)
 
         if p.returncode:
@@ -27,7 +27,7 @@ def check_kconfig(pkgnames):
 
 
 def check_kconfig_all():
-    p = subprocess.run(["pmbootstrap", "kconfig", "check"], check=False)
+    p = subprocess.run(["pmbootstrap", "kconfig", "check", "--keep-going"], check=False)
     return p.returncode == 0
 
 

.gitlab-ci.yml

@@ -125,8 +125,6 @@ mr-settings:
 # build changed aports
 .build:
   stage: build
-  tags:
-    - saas-linux-large-amd64
   rules:
     - if: $CI_PIPELINE_SOURCE == "merge_request_event" || $CI_COMMIT_REF_PROTECTED == "false"
   before_script:
@@ -152,8 +150,6 @@ build-x86:
 
 build-aarch64:
   extends: .build
-  tags:
-    - saas-linux-large-arm64
   script:
     - .ci/build-aarch64.sh
 

.gitlab/issue_templates/Change_Kernel_Config.md

@@ -0,0 +1,31 @@
+<!-- Use this template to kick off the discussion for changing one or more
+     related kernel config options.
+-->
+
+### Read the fine manual, please :)
+
+- [ ] I have read https://postmarketos.org/kconfig-adjust-multiple
+
+### What benefit does the change have?
+
+### Which option(s) would you like to change?
+
+<!-- Make sure to specify if you would like to enable/disable/set a value. -->
+
+### Did you already test that this works as expected?
+
+<!-- Not required, but recommended. If you did test it, please list which
+     device you have tested it with. -->
+
+### For which kernel configs would you do the change?
+
+<!-- If it makes sense, we encourage to adjust all kernels used by devices in
+     the main and community categories, so devices behave consistently. -->
+
+- [ ] all in main and community
+- [ ] certain SoC(s):
+- [ ] other (please specify):
+
+
+<!-- leave this, so it applies the correct label in gitlab -->
+/label ~"change-kernel-config"

.gitlab/issue_templates/Default.md

@@ -28,7 +28,6 @@
 -->
 * [ ] edge (`master` branch)
 * [ ] `v24.06`
-* [ ] `v23.12` (supported until 2024-07-16)
 
 * [ ] I confirm that the issue still is present after running `sudo apk upgrade -a`
 

CODEOWNERS

@@ -31,6 +31,7 @@ device/*/*-pine64-pinephonepro/			@PsychoGame
 device/*/*-pine64-rockpro64/			@PureTryOut
 device/*/*-purism-librem5/			@craftyguy @alistair23 @Newbyte
 device/*/*-qcom-msm8916/			@Minecrell @TravMurav
+device/*/*-qcom-sdm670/				@flamingradian
 device/*/*-qcom-sdm845/				@sdm845-mainline
 device/*/*-qcom-sm6350/				@z3ntu
 device/*/*-samsung-a3/				@Mis012 @TravMurav @Minecrell
@@ -57,12 +58,14 @@ device/*/*-xiaomi-vince/			@M0Rf30
 device/*/*-xiaomi-wt88047/			@Minecrell
 device/*/*-xiaomi-ysl/				@barni2000
 device/*/alsa-ucm-conf-cros/			@WeirdTreeThing
+device/*/alsa-ucm-conf-qcom-sdm670/		@flamingradian
 device/*/device-fairphone-*/			@z3ntu
 device/*/device-generic-x86_64/			@craftyguy @ollieparanoid
 device/*/device-google-nyan-big/		@jenneron
 device/*/device-google-nyan-blaze/		@jenneron
 device/*/device-google-peach-pi/		@jenneron
 device/*/device-google-peach-pit/		@jenneron
+device/*/device-google-sargo/			@flamingradian
 device/*/device-google-snow/			@jenneron
 device/*/device-huawei-plank/			@gtrxAC
 device/*/device-lg-judyln/			@Newbyte
@@ -78,6 +81,7 @@ device/*/device-qemu-aarch64/			@Minecrell @ollieparanoid
 device/*/device-qemu-amd64/			@Minecrell @ollieparanoid
 device/*/device-qemu-riscv64/			@Minecrell @z3ntu
 device/*/device-qualcomm-sdm845/		@calebccff
+device/*/device-raspberry-pi3/			@fossdd
 device/*/device-samsung-chagallwifi/		@Grimler
 device/*/device-samsung-coreprimevelte/		@legolivesmatter @balejk
 device/*/device-samsung-j5y17lte/	@andrisas
@@ -86,6 +90,7 @@ device/*/device-samsung-lt01/			@knuxify
 device/*/device-samsung-m0/			@Newbyte
 device/*/device-samsung-manta/			@jenneron @alexmrqt
 device/*/device-shift-axolotl/			@amartinz @calebccff @dylanvanassche
+device/*/firmware-google-sargo/			@flamingradian
 device/*/firmware-google-veyron-brcm/		@jenneron
 device/*/firmware-odroid-xu4/			@Grimler
 device/*/firmware-oneplus-sdm845/		@calebccff

cross/gcc-aarch64/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-aarch64
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for aarch64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -338,7 +339,7 @@ build() {
 	i586-*-*-*)		_arch_configure="--with-arch=pentium-m --with-fpmath=sse --with-tune=generic --enable-cld";;
 	s390x-*-*-*)		_arch_configure="--with-arch=z196 --with-tune=zEC12 --with-zarch --with-long-double-128 --enable-decimal-float";;
 	riscv64-*-*-*)		_arch_configure="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic";;
-	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d";;
+	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d --with-tls=trad";;
 	esac
 
 	case "$CTARGET_ARCH" in
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-aarch64/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-armhf/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armhf
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for armhf"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -338,7 +339,7 @@ build() {
 	i586-*-*-*)		_arch_configure="--with-arch=pentium-m --with-fpmath=sse --with-tune=generic --enable-cld";;
 	s390x-*-*-*)		_arch_configure="--with-arch=z196 --with-tune=zEC12 --with-zarch --with-long-double-128 --enable-decimal-float";;
 	riscv64-*-*-*)		_arch_configure="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic";;
-	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d";;
+	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d --with-tls=trad";;
 	esac
 
 	case "$CTARGET_ARCH" in
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-armhf/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-armv7/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armv7
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for armv7"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -338,7 +339,7 @@ build() {
 	i586-*-*-*)		_arch_configure="--with-arch=pentium-m --with-fpmath=sse --with-tune=generic --enable-cld";;
 	s390x-*-*-*)		_arch_configure="--with-arch=z196 --with-tune=zEC12 --with-zarch --with-long-double-128 --enable-decimal-float";;
 	riscv64-*-*-*)		_arch_configure="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic";;
-	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d";;
+	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d --with-tls=trad";;
 	esac
 
 	case "$CTARGET_ARCH" in
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-armv7/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-riscv64/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-riscv64
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for riscv64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -338,7 +339,7 @@ build() {
 	i586-*-*-*)		_arch_configure="--with-arch=pentium-m --with-fpmath=sse --with-tune=generic --enable-cld";;
 	s390x-*-*-*)		_arch_configure="--with-arch=z196 --with-tune=zEC12 --with-zarch --with-long-double-128 --enable-decimal-float";;
 	riscv64-*-*-*)		_arch_configure="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic";;
-	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d";;
+	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d --with-tls=trad";;
 	esac
 
 	case "$CTARGET_ARCH" in
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-riscv64/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-x86/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-x86
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for x86"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -338,7 +339,7 @@ build() {
 	i586-*-*-*)		_arch_configure="--with-arch=pentium-m --with-fpmath=sse --with-tune=generic --enable-cld";;
 	s390x-*-*-*)		_arch_configure="--with-arch=z196 --with-tune=zEC12 --with-zarch --with-long-double-128 --enable-decimal-float";;
 	riscv64-*-*-*)		_arch_configure="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic";;
-	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d";;
+	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d --with-tls=trad";;
 	esac
 
 	case "$CTARGET_ARCH" in
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-x86/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-x86_64/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-x86_64
-pkgrel=0
+pkgrel=2
 pkgdesc="Stage2 cross-compiler for x86_64"
 url="https://gcc.gnu.org"
 arch="aarch64"
@@ -278,6 +278,7 @@ source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkg
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -338,7 +339,7 @@ build() {
 	i586-*-*-*)		_arch_configure="--with-arch=pentium-m --with-fpmath=sse --with-tune=generic --enable-cld";;
 	s390x-*-*-*)		_arch_configure="--with-arch=z196 --with-tune=zEC12 --with-zarch --with-long-double-128 --enable-decimal-float";;
 	riscv64-*-*-*)		_arch_configure="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic";;
-	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d";;
+	loongarch64-*-*-*)      _arch_configure="--with-arch=loongarch64 --with-abi=lp64d --with-tls=trad";;
 	esac
 
 	case "$CTARGET_ARCH" in
@@ -837,4 +838,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-x86_64/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/musl-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-aarch64
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-aarch64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-5ad546aca584d77f6fcf7d92bc5e6432d8c32b3db2922a4099423649e674b5c149464bd0048021e50b18398a00382bbeb6a0a598148bea4fa6d783f5c4c4445d  musl-1.2.5-r1-aarch64-edge.apk
-b6fed1441c0eacfea0061967915a876ce0af79b83511d9b05ae7e7cf489d88e36a544fa7f7512f390429d7d0217b672c04a83dfceea603ce0e86d2a47c50f4cc  musl-dev-1.2.5-r1-aarch64-edge.apk
+a3c660153e2cd1859a83e692c4d1c9f92bb442948ec4ed63412ac1d75502fa40a5a383bb548c8ac98d83fdd27f067304e876be1e15f41eaa09f1414cf5d4e189  musl-1.2.5-r2-aarch64-edge.apk
+6e921c1a761125e768e78e072585b226180c1447f04a4d5fc50564787b30f9c1520b3bfe90d835cfba1716fc4672d3df95a0883187adb50627eed9a3c4249a04  musl-dev-1.2.5-r2-aarch64-edge.apk
 "

cross/musl-armhf/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-armhf
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-armhf:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-148883dfd80bb670df4c6a919aaf3334d203a87fac98df8046a920a2e4c1c3439347f5653abc2994e9a9fe2946764395cd83e2f2437ab903e37f8ad3fcc6637a  musl-1.2.5-r1-armhf-edge.apk
-052f4f3ff6974aadbe90c1a69c4b29a1fefc25d2f2f794b3d55ed49b79a94dab900592a65b3c80ae9824580eab4fb99cb2cfdf9399354e74a1804871d97774a0  musl-dev-1.2.5-r1-armhf-edge.apk
+20f07f25e5267acac97f7f7bf98763869c9a193bf44d1ef2b79f46f2e854aeabe2baa74d0311057541fb99179addbd43c08c56d1361ed349ae22973141f639c5  musl-1.2.5-r2-armhf-edge.apk
+4afb4520885704849bec649f5488add0a3a7b25005172d69f03337cf5b0a82d9f564cba11bbfa84a43a9386e027a8516fcc4573210b4e1fe340cc295a7f52499  musl-dev-1.2.5-r2-armhf-edge.apk
 "

cross/musl-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-armv7
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-armv7:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-f3da7602184940c3ca4ddc973fd127fe08eb5e9141cf4c22cf49ccf131ef836b7f697f20dc64c7e18661f88779354c8b93c14521d18fb2e83d10638c3c8ed7d5  musl-1.2.5-r1-armv7-edge.apk
-b2678887dfc565691d92c1604137d984c5ce68f7c39c1ec2fd7200d4df4f818d4690c323f93b76ca1d4498a5dc36dff61959e06cc749099c706f85601d915d8e  musl-dev-1.2.5-r1-armv7-edge.apk
+0a542c678cfc7ed0cc4246985bd1ecce63247ca4db0ea9fde7c1ee2b30f683b46d7c4011b21931d19fc7c3faeb787413d243580417ec90f745b77534277a6f68  musl-1.2.5-r2-armv7-edge.apk
+26516f5ffc1f04223cce8bae2122a2eab17ec59ce1ef0c1d2382394d9dd0e014ac77336639592f24d15f0ec5120ea7b8329febab1bbbaf3dfecb777b944d6337  musl-dev-1.2.5-r2-armv7-edge.apk
 "

cross/musl-riscv64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-riscv64
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-riscv64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-822f24faaf2285174742788da0dceef3bada4dbd0db9f67362876b3c0ab6bc647a0f2f0cc70e2e28dbb90121f08b65640a344e7cae8416a84bfb389db32e7d9c  musl-1.2.5-r1-riscv64-edge.apk
-04ac4a81d713f71b68082767ce2afab3ce458730664c140f49a0b33f257666a6b4289c5b53935fe16345f8445a458e5307511773651c4574526cfaaf232c239a  musl-dev-1.2.5-r1-riscv64-edge.apk
+ebc1f6759f73c492c00429fd735bd1f3f67bb5a1530156f0c0a821f693b415ba7b8807c22134ce8bd4043f18b12356151c4bfaff59946d059cd0523ebc8aad57  musl-1.2.5-r2-riscv64-edge.apk
+d5209392baedcee71455faa51f6a2e60a90b2bc51c1f5f2c9fb03ff6692b246225d8db7dd5f9165d76bd9d2463e797c9b3c805e04887a4b4b90ec55e96ced627  musl-dev-1.2.5-r2-riscv64-edge.apk
 "

cross/musl-x86/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-x86
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-x86:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-53a30a57f0db29e8d73d7190590fce18a19bcd358f9b0f3d4fa0b8821dad4ed5f1065c3c07dbc373a23cbd98c9a9dc1c2c2d864ac88eefd53dc5f89d8e57ed67  musl-1.2.5-r1-x86-edge.apk
-e9178fcfe27bdc7568c35889cff8cf20829f67460fd6dc22a6ca0465063a809081ee1267b4275432d23d1e7d457a4b207a0ff11c678233c4e430a1173d4ccea8  musl-dev-1.2.5-r1-x86-edge.apk
+bde9b17b3f8b696dd863509713113b720bdff8d125e98eed5165f5fa0934d3a8adc317ffb319e3c045b99389ebb0ac08896c0bedd6d0e7461c9f2d98ffee62f9  musl-1.2.5-r2-x86-edge.apk
+cfd0b502e1237024736b6215ac944299664f4b44802533f5cf6b5239a15c22bdc7782004e1485e15d8184ca0cc9afbf704c12cc39d4fe93611f65c8915d595a7  musl-dev-1.2.5-r2-x86-edge.apk
 "

cross/musl-x86_64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-x86_64
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="aarch64"
 subpackages="musl-dev-x86_64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-5506970c66b6da294d32961e94cadc6926a7405915a3d4dd519ed8c2aae829f2fbfaab2ccc8d0794f4aa102aa3e8cbd62099aa54668a11ac0c5072f59befece6  musl-1.2.5-r1-x86_64-edge.apk
-bd2602e59831ba860a548c8281bb62be3382b4035f18c9e36350be644db61a762a413e1d696697d402a57d4bc565faf86c2a212e27c9b9a890d765f794bbe829  musl-dev-1.2.5-r1-x86_64-edge.apk
+2554e2ac0b3f02904197de5317db836e5dbd2631d2ab6e59c3453eeff9b1647b9110005cfe7922470512e7d8b561c94769bf348f7f959754fdb1ca05b403d99b  musl-1.2.5-r2-x86_64-edge.apk
+9a29dcb8cd82da7eb929269c75d2c6637a0ce457526c4960164bcff424f6a0cf581b5a4b2f0020624360d1e5c71b10042dbe59db21df4cd6ffa14b0845c71802  musl-dev-1.2.5-r2-x86_64-edge.apk
 "

device/.shared-patches/linux/fix-check-lxdialog-makefile.patch

@@ -0,0 +1,25 @@
+It seems that newer versions of GNU Make do not allow to use variables before
+defining it.
+
+diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
+index 844bc9da..911c6ba1 100644
+--- a/scripts/kconfig/Makefile
++++ b/scripts/kconfig/Makefile
+@@ -192,6 +192,8 @@ clean-files	+= zconf.tab.c zconf.lex.c zconf.hash.c gconf.glade.h
+ clean-files     += mconf qconf gconf nconf
+ clean-files     += config.pot linux.pot
+ 
++HOSTLOADLIBES_mconf   = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
++
+ # Check that we have the required ncurses stuff installed for lxdialog (menuconfig)
+ PHONY += $(obj)/dochecklxdialog
+ $(addprefix $(obj)/,$(lxdialog)): $(obj)/dochecklxdialog
+@@ -217,8 +219,6 @@ HOSTLOADLIBES_gconf	= `pkg-config --libs gtk+-2.0 gmodule-2.0 libglade-2.0`
+ HOSTCFLAGS_gconf.o	= `pkg-config --cflags gtk+-2.0 gmodule-2.0 libglade-2.0` \
+                           -Wno-missing-prototypes
+ 
+-HOSTLOADLIBES_mconf   = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
+-
+ HOSTLOADLIBES_nconf	= $(shell \
+ 				pkg-config --libs menu panel ncurses 2>/dev/null \
+ 				|| echo "-lmenu -lpanel -lncurses"  )

device/.shared-patches/linux/fix-check-lxdialog.patch

@@ -0,0 +1,15 @@
+Fix pre-ANSI C code in check-lxdialog.sh.
+
+diff --git a/scripts/kconfig/lxdialog/check-lxdialog.sh b/scripts/kconfig/lxdialog/check-lxdialog.sh
+index 9d2a4c58..364eaecb 100644
+--- a/scripts/kconfig/lxdialog/check-lxdialog.sh
++++ b/scripts/kconfig/lxdialog/check-lxdialog.sh
+@@ -43,7 +43,7 @@ trap "rm -f $tmp" 0 1 2 3 15
+ check() {
+         $cc -x c - -o $tmp 2>/dev/null <<'EOF'
+ #include CURSES_LOC
+-main() {}
++int main() { return 0; }
+ EOF
+ 	if [ $? != 0 ]; then
+ 	    echo " *** Unable to find the ncurses libraries or the"       1>&2

device/community/device-fairphone-fp4/APKBUILD

@@ -43,10 +43,14 @@ install="$pkgname.post-install $pkgname.post-upgrade"
 source="
 	81-libssc-fairphone-fp4.rules
 	90-feedbackd-aw8695.rules
+	FP4.yaml
 	deviceinfo
 	hexagonrpcd.confd
 	modules-initfs
 	"
+subpackages="
+	$pkgname-lomiri
+"
 
 build() {
 	devicepkg_build $startdir $pkgname
@@ -63,9 +67,16 @@ package() {
 		"$pkgdir"/etc/conf.d/hexagonrpcd-adsp-sensorspd
 }
 
+lomiri() {
+	install_if="$pkgname=$pkgver-r$pkgrel lomiri"
+	install -Dm644 "$srcdir"/FP4.yaml \
+		"$subpkgdir"/etc/lomiri-deviceinfo/devices/FP4.yaml
+}
+
 sha512sums="
 2c16ba75e0077b2b1eaefa4c73b287475505a1aeb291ec29316d41cc094277320f9d2aaabfd91eb1dc0f488ab2d61a94faef16e7afe0f1e226779113761b9a37  81-libssc-fairphone-fp4.rules
 2974ccc172bf1299daeb0bc746879b3a1db1fbc3a2b163a02a6554fed6ed9f733144bcf976cd2441c5664d496dcce3ae943f4314c653470dc07dda0de5ad632b  90-feedbackd-aw8695.rules
+1d7d59c513df6cebd15671b868a1f57dd0f407492de352efdbf89bac2ae1ca752d8cdc346f5d24aa2d324ce13ad23352543c94371c477fac278123020f8b2d1c  FP4.yaml
 9549f105f865d230e7b67819c96b7e06a5ed4d5808f083099a408934ffbacdb412984b861f6756fa4fde94b51e6a268b8d2ce9fed6f13ee3e8041bb96492310a  deviceinfo
 6a3d620f2cc60308a62ff651ffb00a5ee1f092131cca9d33b6afd61c8a372a3fd7d46540162213593107e0943b33f3f0119d003d43dcd06dbde757390a6c1729  hexagonrpcd.confd
 52bb7ed829caa4dcff9728bd6e3cdf118b3c7ee7dfe90df0d4e6422dd67bf3258ae2a4d2dc7599da4182fbd8eb47a0e1d20c58198dc17f2bf178b8f01a8887f7  modules-initfs

device/community/device-fairphone-fp4/FP4.yaml

@@ -0,0 +1,8 @@
+FP4:
+  Names:
+    - Fairphone 4
+  PrettyName: Fairphone 4
+  DeviceType: phone
+  GridUnit: 21
+  PrimaryOrientation: Portrait
+  # SensorfwConfig: /etc/deviceinfo/sensorfw/pinephone.conf

device/community/device-generic-x86_64/30-gpu-firmware.files

@@ -0,0 +1,4 @@
+# Newer integrated and discrete Intel GPUs won't work without GUC fw,
+# and older GPUs need DMC firmware for lower power states, so let's
+# include everything:
+/lib/firmware/i915

device/community/device-generic-x86_64/APKBUILD

@@ -2,7 +2,7 @@
 # Co-Maintainer: Oliver Smith <ollieparanoid@postmarketos.org>
 pkgname=device-generic-x86_64
 pkgdesc="Generic x86_64 system, with EFI"
-pkgver=14
+pkgver=15
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -17,6 +17,7 @@ makedepends="devicepkg-dev"
 source="
 	deviceinfo
 	modules-initfs
+	30-gpu-firmware.files
 "
 install="$pkgname.post-install $pkgname.post-upgrade"
 subpackages="
@@ -40,6 +41,9 @@ build() {
 
 package() {
 	devicepkg_package $startdir $pkgname
+
+	install -Dm644 "$srcdir"/30-gpu-firmware.files \
+		-t "$pkgdir"/usr/share/mkinitfs/files/
 }
 
 kernel_edge() {
@@ -61,4 +65,5 @@ kernel_lts() {
 sha512sums="
 e9dfcd70ccfb9a0fdaa0cdc52faf3be96d6de8af8c60a758bb703c515b0648cec4552e0eaf56e5168b0004cd3fc4b28118abb05dad2c581d3579a2e9134862cb  deviceinfo
 e464ef0ad4a4c34d2d53f69c4612b612ea878a77c9efdef69b0f842edf701036c8218809fd63aac286d6a08ae07f39e568199fc3e38d145e716c1723e7215019  modules-initfs
+9599a10679a43929e4ed2ea22269a0716219163817574d48db4dc1cb21a0fcf17ea54d77d5fd8efd034905c421ecb3eaa600a72927d683983ce48d1159329881  30-gpu-firmware.files
 "

device/community/device-google-gru/APKBUILD

@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-gru
 pkgdesc="Google Gru Chromebooks"
-pkgver=6
+pkgver=7
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -53,6 +53,6 @@ nonfree_firmware() {
 
 
 sha512sums="
-6a8aba7e13f864a223a658f724ad8ff6c04ed986a747439cf88a6365c5fa037da9fb4950fa94794eff64937979f988015af9d0a6359deb041d1a2b128baac75e  deviceinfo
+7815e3a164720b5ad0df7ce8d12b12fe85cc4bb7bf4a09ccc0eb831a58a920026fd92d545f4d6fb459a688e15b9d542e360fd597cd5d3b01a3ea338c3928d2a3  deviceinfo
 a750a0c41068082e0b82351d5aec91715e1a5215b09b26fec644dfe259cea2d662e878433a732a8c06dab2a9b420baec2bcc6161d8357cf3ed770239c5165090  modules-initfs
 "

device/community/device-google-gru/deviceinfo

@@ -25,5 +25,6 @@ deviceinfo_cgpt_kpart="/boot/vmlinuz.kpart"
 deviceinfo_cgpt_kpart_start="8192"
 deviceinfo_cgpt_kpart_size="65536"
 deviceinfo_depthcharge_board="gru"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
 deviceinfo_generate_extlinux_config="true"

device/community/device-google-kukui/APKBUILD

@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-kukui
 pkgdesc="Google Kukui Chromebooks"
-pkgver=7
+pkgver=8
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -14,7 +14,6 @@ depends="
 	linux-postmarketos-mediatek-mt8183>=6.1.28-r0
 	postmarketos-base
 	postmarketos-cros-common
-	postmarketos-initramfs-minimal
 	soc-mediatek-mt8183
 "
 makedepends="devicepkg-dev"
@@ -74,6 +73,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-e1c88545563aa40b69f79ed1d86b4da0d7ad65dfff07dce05f56d51b442ad9bae27ae2d27afa2f5131309072a9ea4f3b026d498ab067b315ed0719a3dded4b2c  deviceinfo
+ecd503069ecf272ddc238bd49dc257a1f3e0f4c20b322238e2da83104b94b331c22886d1591b6fe0b78c986e15ac6251e364ec1b750f9125ea722a6b1a79e2b8  deviceinfo
 8e95624610dae7d18684056396c9e82635ddce7303d6770e965f9372ffa101fdfd5f8337bc7368004890e9836798663a98c142c52ed63795877ea37ac8da56af  modules-initfs
 "

device/community/device-google-kukui/deviceinfo

@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="65536"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8183"
 # board here.
 deviceinfo_depthcharge_board="mt8183"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"

device/community/device-google-oak/APKBUILD

@@ -3,7 +3,7 @@
 # Co-Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-oak
 pkgdesc="Google Oak Chromebooks"
-pkgver=5
+pkgver=6
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -40,6 +40,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-ebf7ed07ffcfe30c01c717db00c255e2c650339bace70afffcac4566267da8b6d3e22f819601be2ee355d2c1f56b01e37fca5566a2517fc1ffb642e530b674fb  deviceinfo
+d082e6c155347f662403f611f44c3eddb2a0548397bec4f29b882f371a18efa9c2628a88599b19c0c58c1886d0c25035367f02651a60fb6c3293faa1449b83d5  deviceinfo
 4b0197eacfeeb4b13f5abc26950f570ee762742547674ce10110ccea63eb46630a2e3b5f87e9c9a1f9deda21baf05bec248ab7a65656687ec94d296b5657dafa  modules-initfs
 "

device/community/device-google-oak/deviceinfo

@@ -33,4 +33,5 @@ deviceinfo_cgpt_kpart_size="65536"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8173"
 # board here.
 deviceinfo_depthcharge_board="mt8173"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"

device/community/device-google-sargo/APKBUILD

@@ -3,7 +3,7 @@
 pkgname=device-google-sargo
 pkgdesc="Google Pixel 3a"
 pkgver=6
-pkgrel=0
+pkgrel=1
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -28,7 +28,10 @@ source="
 	no-hexagonrpcd-on-suspend.sh
 	q6voiced.conf
 "
-subpackages="$pkgname-nonfree-firmware:nonfree_firmware"
+subpackages="
+	$pkgname-camera
+	$pkgname-nonfree-firmware:nonfree_firmware
+	"
 
 build() {
 	devicepkg_build $startdir $pkgname
@@ -43,6 +46,12 @@ package() {
 		"$pkgdir"/etc/unl0kr.conf.d/10-unl0kr-msm.conf
 }
 
+camera() {
+	install_if="$pkgname=$pkgver-r$pkgrel postmarketos-default-camera"
+	depends="snapshot"
+	mkdir -p "$subpkgdir"
+}
+
 nonfree_firmware() {
 	pkgdesc="Proprietary firmware blobs for the Google Pixel 3a"
 	replaces="hexagonrpcd-openrc"

device/community/device-google-trogdor/APKBUILD

@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-trogdor
 pkgdesc="Google Trogdor Chromebooks"
-pkgver=2
+pkgver=3
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -44,6 +44,6 @@ nonfree_firmware() {
 
 
 sha512sums="
-e2eee558c89272358b4531ef9d7b7cefc937702c17985c3067181029a7f2c8545f68c3634d515fee6d12229d09f52b6f2b4ae804449f37c11b3aa9e5bcfaaced  deviceinfo
+0a40c43eda1dbb159da59c00b3a1e51fff299a29add210de4d9a16c060da523c358b6d821aa1dd16523bb912d00e1a1837193cce52415f329ac2e171d220f6d3  deviceinfo
 ef0257928f28aff25e6c625fabfd0942b01d4d86f1b523212ca825cf80f8b7a6c20ff17bfb02cb19f2a5d8787326ba22ad560a957c8d3c38b9ec70f1e16f9117  modules-initfs
 "

device/community/device-google-trogdor/deviceinfo

@@ -33,4 +33,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "qc7180"
 # board here.
 deviceinfo_depthcharge_board="qc7180"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"

device/community/device-oneplus-enchilada/APKBUILD

@@ -4,7 +4,7 @@
 pkgname=device-oneplus-enchilada
 pkgdesc="OnePlus 6"
 pkgver=14
-pkgrel=0
+pkgrel=1
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -26,7 +26,11 @@ source="
 	q6voiced.conf
 	81-libssc-oneplus-enchilada.rules
 "
-subpackages="$pkgname-nonfree-firmware:nonfree_firmware $pkgname-pmtest"
+subpackages="
+	$pkgname-nonfree-firmware-openrc:nonfree_firmware_openrc
+	$pkgname-nonfree-firmware:nonfree_firmware
+	$pkgname-pmtest
+"
 
 build() {
 	devicepkg_build $startdir $pkgname
@@ -47,12 +51,16 @@ nonfree_firmware() {
 		soc-qcom-sdm845-nonfree-firmware
 		soc-qcom-sdm845-modem
 	"
+
+	install -Dm644 "$srcdir"/81-libssc-oneplus-enchilada.rules -t "$subpkgdir"/usr/lib/udev/rules.d/
+}
+
+nonfree_firmware_openrc() {
+	install_if="$pkgname-nonfree-firmware=$pkgver-r$pkgrel"
 	replaces="hexagonrpcd-openrc"
 	install="$subpkgname.post-install $subpkgname.post-upgrade"
-	mkdir "$subpkgdir"
 
 	install -Dm644 q6voiced.conf "$subpkgdir"/etc/conf.d/q6voiced
-	install -Dm644 "$srcdir"/81-libssc-oneplus-enchilada.rules -t "$subpkgdir"/usr/lib/udev/rules.d/
 	install -Dm644 "$srcdir"/hexagonrpcd.confd "$subpkgdir"/etc/conf.d/hexagonrpcd-sdsp
 }
 

device/community/device-oneplus-enchilada/device-oneplus-enchilada-nonfree-firmware-openrc.post-upgrade

@@ -0,0 +1 @@
+device-oneplus-enchilada-nonfree-firmware-openrc.post-install

device/community/device-oneplus-enchilada/device-oneplus-enchilada-nonfree-firmware.post-upgrade

@@ -1 +0,0 @@
-device-oneplus-enchilada-nonfree-firmware.post-install

device/community/device-shift-axolotl/APKBUILD

@@ -5,7 +5,7 @@
 pkgname=device-shift-axolotl
 pkgdesc="SHIFT6mq"
 pkgver=15
-pkgrel=0
+pkgrel=1
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -30,6 +30,7 @@ source="
 "
 subpackages="
 	$pkgname-nonfree-firmware:nonfree_firmware
+	$pkgname-nonfree-firmware-openrc:nonfree_firmware_openrc
 	$pkgname-pmtest
 "
 
@@ -49,12 +50,16 @@ nonfree_firmware() {
 		soc-qcom-sdm845-nonfree-firmware
 		soc-qcom-sdm845-modem
 	"
+
+	install -Dm644 "$srcdir"/81-libssc-shift-axolotl.rules -t "$subpkgdir"/usr/lib/udev/rules.d/
+}
+
+nonfree_firmware_openrc() {
+	install_if="$pkgname-nonfree-firmware=$pkgver-r$pkgrel openrc"
 	replaces="hexagonrpcd-openrc"
 	install="$subpkgname.post-install $subpkgname.post-upgrade"
-	mkdir "$subpkgdir"
 
 	install -Dm644 q6voiced.conf "$subpkgdir"/etc/conf.d/q6voiced
-	install -Dm644 "$srcdir"/81-libssc-shift-axolotl.rules -t "$subpkgdir"/usr/lib/udev/rules.d/
 	install -Dm644 "$srcdir"/hexagonrpcd.confd "$subpkgdir"/etc/conf.d/hexagonrpcd-sdsp
 }
 

device/community/device-shift-axolotl/device-shift-axolotl-nonfree-firmware-openrc.post-upgrade

@@ -0,0 +1 @@
+device-shift-axolotl-nonfree-firmware-openrc.post-install

device/community/device-shift-axolotl/device-shift-axolotl-nonfree-firmware.post-upgrade

@@ -1 +0,0 @@
-device-shift-axolotl-nonfree-firmware.post-install

device/community/firmware-shift-sdm845/APKBUILD

@@ -2,7 +2,7 @@
 
 pkgname=firmware-shift-sdm845
 pkgver=20240517
-pkgrel=0
+pkgrel=1
 pkgdesc="Firmware for SHIFT sdm845 devices"
 url="https://gitlab.com/sdm845-mainline/firmware-shift-sdm845"
 arch="aarch64"
@@ -33,8 +33,8 @@ package() {
 	done < "$srcdir/firmware.files"
 
 	# Install symlinks for using upstream firmware
-	ln -s ../mba.mbn "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/mba.mbn
-	ln -s ../../../ath10k/WCN3990/hw1.0/wlanmdsp.mbn "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/wlanmdsp.mbn
+	ln -s ../mba.mbn.zst "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/mba.mbn.zst
+	ln -s ../../../ath10k/WCN3990/hw1.0/wlanmdsp.mbn.zst "$pkgdir"/lib/firmware/qcom/sdm845/axolotl/wlanmdsp.mbn.zst
 }
 
 pmtest() {

device/community/linux-postmarketos-exynos4/APKBUILD

@@ -4,8 +4,8 @@
 # Kernel config based on: arch/arm/configs/exynos_defconfig
 
 pkgname=linux-postmarketos-exynos4
-pkgver=6.7.6
-pkgrel=6
+pkgver=6.10.0
+pkgrel=0
 pkgdesc="Mainline kernel fork for Samsung Exynos4 devices"
 arch="armv7"
 _carch="arm"
@@ -41,23 +41,11 @@ _tag="v${pkgver//_/-}-exynos4"
 source="
 	$pkgname-$_tag.tar.bz2::$url/-/archive/$_tag/linux-$_tag.tar.bz2
 	$_config
-	initramfs.list
-	init
-	tab3-limit-memory.patch
 "
 builddir="$srcdir/linux-$_tag"
 
-prepare_isorec() {
-	# https://wiki.postmarketos.org/wiki/Boot_process#isorec
-	cp -v /usr/$(arch_to_hostspec $arch)/bin/busybox.static \
-		"$builddir"/usr/
-	cp -v "$srcdir"/init "$builddir"/usr/
-	cp -v "$srcdir"/initramfs.list "$builddir"/usr/
-}
-
 prepare() {
 	default_prepare
-	prepare_isorec
 	cp -v "$srcdir/$_config" .config
 }
 
@@ -81,9 +69,6 @@ package() {
 }
 
 sha512sums="
-705cd617d135900cb25c8b6da7177d507e6a179b521e04aeae18080995514cbd69381a21f942ebf4d8cee427e3c60d53e6a06ed918ddcaacc243ca585ef61c11  linux-postmarketos-exynos4-v6.7.6-exynos4.tar.bz2
-4de127f68b56c380455f77610fcd6b0fd2ed8b79355fa9050ac90b0b2a9d5ad9fe3f5e81f304f8e3327e0203866ded2d6eae083847670eaa9fbdb156b50db9b8  config-postmarketos-exynos4.armv7
-aaff0332b90e1f9f62de1128cace934717336e54ab09de46477369fa808302482d97334e43a85ee8597c1bcab64d3484750103559fea2ce8cd51776156bf7591  initramfs.list
-09f1f214a24300696809727a7b04378887c06ca6f40803ca51a12bf2176a360b2eb8632139d6a0722094e05cb2038bdb04018a1e3d33fc2697674552ade03bee  init
-aea665e80dee318ec3be23d3f28b88e87eb551d2756e14d896781a0861a4387920f6969990eb171e8c7d6f86c36cef63a89337d63bfee7e44b9de7a8efb36c73  tab3-limit-memory.patch
+a320d0be4532f469be015e2a6706e507e89daaa55ad50d57a56451dca04b6bbea56f62d15877ef000027ce887ecd04257f9c71d7c9d80aab55607494205fa5c7  linux-postmarketos-exynos4-v6.10.0-exynos4.tar.bz2
+2dc3a1d57bf485b513308362b263de59dd4ee507f9a23935a91f7bee9fb119a172089b5b64b364a770e378e225e253424eacad6905e9f1be57231d4ed5cf7b9f  config-postmarketos-exynos4.armv7
 "

device/community/linux-postmarketos-exynos4/init

@@ -1,20 +0,0 @@
-#!/bin/busybox sh
-
-# Samsung kernels come with their own initramfs, which extract and load another
-# initramfs. Usually that depends on the recovery key combination being pressed
-# or not. For simplicity, we always boot the recovery image (from the recovery
-# partition) here.
-echo "### isorec initramfs ###"
-busybox mount -t proc proc /proc
-busybox mount -t sysfs sysfs /sys
-
-# always use the "isorec"-style lzop compressed initramfs
-# from the recovery partition
-load_image=/isorec.cpio
-busybox lzop -dc /dev/block/mmcblk0p6 > ${load_image}
-busybox cpio -iu < ${load_image}
-busybox rm ${load_image}
-
-busybox umount /sys
-busybox umount /proc
-exec /init

device/community/linux-postmarketos-exynos4/initramfs.list

@@ -1,21 +0,0 @@
-dir /dev 755 0 0
-dir /dev/block 755 0 0
-nod /dev/block/mmcblk0 600 0 0 b 179 0
-nod /dev/block/mmcblk0p1 600 0 0 b 179 1
-nod /dev/block/mmcblk0p2 600 0 0 b 179 2
-nod /dev/block/mmcblk0p3 600 0 0 b 179 3
-nod /dev/block/mmcblk0p4 600 0 0 b 179 4
-nod /dev/block/mmcblk0p5 600 0 0 b 179 5
-nod /dev/block/mmcblk0p6 600 0 0 b 179 6
-nod /dev/block/mmcblk0p7 600 0 0 b 179 7
-nod /dev/block/mmcblk0p8 600 0 0 b 179 8
-nod /dev/block/mmcblk0p9 600 0 0 b 179 9
-nod /dev/block/mmcblk0p10 600 0 0 b 179 10
-nod /dev/block/mmcblk0p11 600 0 0 b 179 11
-nod /dev/block/mmcblk0p12 600 0 0 b 179 12
-nod /dev/console 600 0 0 c 5 1
-dir /bin 755 0 0
-dir /proc 755 0 0
-dir /sys 755 0 0
-file /bin/busybox usr/busybox.static 755 0 0
-file /init usr/init 755 0 0

device/community/linux-postmarketos-exynos4/tab3-limit-memory.patch

@@ -1,36 +0,0 @@
-From 57ae04aa40be1e83e2da2fdf92de749f694ea5f8 Mon Sep 17 00:00:00 2001
-From: Artur Weber <aweber.kernel@gmail.com>
-Date: Sat, 17 Feb 2024 12:34:46 +0100
-Link: https://gitlab.com/exynos4-mainline/linux/-/merge_requests/13
-Subject: [PATCH] ARM: dts: exynos4212-tab3: Limit usable memory range
-
-The stock bootloader on the Samsung Galaxy Tab 3 8.0 provides an
-incorrect available memory range over ATAG_MEM. Limit the usable
-memory in the DTS to prevent it from doing so, without having to
-disable ATAG support.
-
-Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
----
- arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
-index 87a1317f9220..996cd5cb0c07 100644
---- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
-+++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
-@@ -45,6 +45,12 @@ chosen {
- 		/* Default S-BOOT bootloader loads initramfs here */
- 		linux,initrd-start = <0x42000000>;
- 		linux,initrd-end = <0x42800000>;
-+
-+		/*
-+		 * S-BOOT provides incorrect memory size in bootloader;
-+		 * override it here
-+		 */
-+		linux,usable-memory-range = <0x40000000 0x3fc00000>;
- 	};
- 
- 	firmware@204f000 {
--- 
-2.44.0
-

device/community/linux-postmarketos-mediatek-mt8173/APKBUILD

@@ -1,7 +1,7 @@
 # Maintainer: Adam Thiede <me@adamthiede.com>
 # Co-Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=linux-postmarketos-mediatek-mt8173
-pkgver=6.10.3
+pkgver=6.10.6
 pkgrel=0
 pkgdesc="Mainline kernel fork for Mediatek MT8173 devices"
 arch="aarch64"
@@ -39,6 +39,7 @@ source="
 	fix-mmc1-speed.patch
 	fix-mmc-order.patch
 	fix-spi-nor-max-frequency.patch
+	temp-fix-build-error.patch
 "
 builddir="$srcdir/linux-${_kernver//_/-}"
 
@@ -68,9 +69,10 @@ package() {
 }
 
 sha512sums="
-dd6061c5871d7b313e1b0eec791444b911f9d9d5e28b1d7a81a265708688808c157adfba92459511e9b786d09e3f96f5bc3c03980360061344ad8e225e165f6a  linux-6.10.3.tar.xz
-4389a117008b0f27ed7dc00aac69ae50c7f30f5684861e9e1ede6658b00c7a16720fe8ffe1621c1a3c80cde5cfdc05301bdb2e029234808a289c7c4890149983  config-postmarketos-mediatek-mt8173.aarch64
+991ec7c7d2d490cb90b182a29e892dae586918eee7f3ff4b6e26f4ff9b31b6d7a31cdc31d25ca12243ecab59787aad75f0056b2fbe6997d0dfd68c357e7703af  linux-6.10.6.tar.xz
+c38ad0e98f763b1c3ece2f764ff6aed4dedf3064673a981c238ced9e0b51ce417375360ca86a471c1e53e11e838fec4b7540f21ecd9a8699e57352e22c941f6d  config-postmarketos-mediatek-mt8173.aarch64
 4b499c1fbf53631cffd6fa7299643dc744e0e2187f71804664b02f05296162b42e3f76aa0d8c688cecb43a8bcd41ec92991c98287951292260237b828dcca710  fix-mmc1-speed.patch
 c86f8dfc32165a32381d45a4c8b6811ebf43f01b5d8a48fbe227cf5084cfefe24b32264c1c150cb49115db4759a2d21ad48b37dcaac78367d226e9cc2a5ba849  fix-mmc-order.patch
 caf48ac0f77661153ee94c7de4931baca135a69a97e93f01ad8f276b4a9944e077d7214c117450943cca07990c773661f79718cb0c2ff7c5789c93d37afb26de  fix-spi-nor-max-frequency.patch
+9842da152a3dd95054f6f0110c8b942935645ab5c6fbd07300021212ce477e70c85da56d54ceecc189378c0b4adc7a699068d6bc86bd5a67140565b1535f3af5  temp-fix-build-error.patch
 "

device/community/linux-postmarketos-mediatek-mt8173/config-postmarketos-mediatek-mt8173.aarch64

@@ -1,18 +1,21 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 6.10.3 Kernel Configuration
+# Linux/arm64 6.10.6 Kernel Configuration
 #
-CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 14.2.0) 14.2.0"
+CONFIG_CC_VERSION_TEXT="gcc (Alpine 14.2.0) 14.2.0"
 CONFIG_CC_IS_GCC=y
 CONFIG_GCC_VERSION=140200
 CONFIG_CLANG_VERSION=0
 CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=24200
+CONFIG_AS_VERSION=24301
 CONFIG_LD_IS_BFD=y
-CONFIG_LD_VERSION=24200
+CONFIG_LD_VERSION=24301
 CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
 CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_TOOLS_SUPPORT_RELR=y
 CONFIG_CC_HAS_ASM_INLINE=y
 CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
 CONFIG_PAHOLE_VERSION=0
@@ -390,7 +393,6 @@ CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
 CONFIG_ARM64_ERRATUM_2966298=y
 CONFIG_ARM64_ERRATUM_3117295=y
 # CONFIG_ARM64_ERRATUM_3194386 is not set
-# CONFIG_ARM64_ERRATUM_3312417 is not set
 CONFIG_CAVIUM_ERRATUM_22375=y
 CONFIG_CAVIUM_ERRATUM_23144=y
 CONFIG_CAVIUM_ERRATUM_23154=y
@@ -754,6 +756,7 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
 CONFIG_ARCH_USE_MEMREMAP_PROT=y
 # CONFIG_LOCK_EVENT_COUNTS is not set
 CONFIG_ARCH_HAS_RELR=y
+# CONFIG_RELR is not set
 CONFIG_HAVE_PREEMPT_DYNAMIC=y
 CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
 CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y

device/community/linux-postmarketos-mediatek-mt8173/temp-fix-build-error.patch

@@ -0,0 +1,100 @@
+From 7258fdd7d7459616b3fe1a603e33900584b10c13 Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <masahiroy@kernel.org>
+Date: Sat, 10 Aug 2024 01:07:20 +0900
+Subject: [PATCH] tty: vt: conmakehash: remove non-portable code printing
+ comment header
+
+Commit 6e20753da6bc ("tty: vt: conmakehash: cope with abs_srctree no
+longer in env") included <linux/limits.h>, which invoked another
+(wrong) patch that tried to address a build error on macOS.
+
+According to the specification [1], the correct header to use PATH_MAX
+is <limits.h>.
+
+The minimal fix would be to replace <linux/limits.h> with <limits.h>.
+
+However, the following commits seem questionable to me:
+
+ - 3bd85c6c97b2 ("tty: vt: conmakehash: Don't mention the full path of the input in output")
+ - 6e20753da6bc ("tty: vt: conmakehash: cope with abs_srctree no longer in env")
+
+These commits made too many efforts to cope with a comment header in
+drivers/tty/vt/consolemap_deftbl.c:
+
+  /*
+   * Do not edit this file; it was automatically generated by
+   *
+   * conmakehash drivers/tty/vt/cp437.uni > [this file]
+   *
+   */
+
+With this commit, the header part of the generate C file will be
+simplified as follows:
+
+  /*
+   * Automatically generated file; Do not edit.
+   */
+
+BTW, another series of excessive efforts for a comment header can be
+seen in the following:
+
+ - 5ef6dc08cfde ("lib/build_OID_registry: don't mention the full path of the script in output")
+ - 2fe29fe94563 ("lib/build_OID_registry: avoid non-destructive substitution for Perl < 5.13.2 compat")
+
+[1]: https://pubs.opengroup.org/onlinepubs/009695399/basedefs/limits.h.html
+
+Fixes: 6e20753da6bc ("tty: vt: conmakehash: cope with abs_srctree no longer in env")
+Cc: stable <stable@kernel.org>
+Reported-by: Daniel Gomez <da.gomez@samsung.com>
+Closes: https://lore.kernel.org/all/20240807-macos-build-support-v1-11-4cd1ded85694@samsung.com/
+Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
+Link: https://lore.kernel.org/r/20240809160853.1269466-1-masahiroy@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/vt/conmakehash.c | 12 ++----------
+ 1 file changed, 2 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/tty/vt/conmakehash.c b/drivers/tty/vt/conmakehash.c
+index 82d9db68b2ce81..a931fcde7ad98d 100644
+--- a/drivers/tty/vt/conmakehash.c
++++ b/drivers/tty/vt/conmakehash.c
+@@ -11,8 +11,6 @@
+  * Copyright (C) 1995-1997 H. Peter Anvin
+  */
+ 
+-#include <libgen.h>
+-#include <linux/limits.h>
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <sysexits.h>
+@@ -79,7 +77,6 @@ int main(int argc, char *argv[])
+ {
+   FILE *ctbl;
+   const char *tblname;
+-  char base_tblname[PATH_MAX];
+   char buffer[65536];
+   int fontlen;
+   int i, nuni, nent;
+@@ -245,20 +242,15 @@ int main(int argc, char *argv[])
+   for ( i = 0 ; i < fontlen ; i++ )
+     nuni += unicount[i];
+ 
+-  strncpy(base_tblname, tblname, PATH_MAX);
+-  base_tblname[PATH_MAX - 1] = 0;
+   printf("\
+ /*\n\
+- * Do not edit this file; it was automatically generated by\n\
+- *\n\
+- * conmakehash %s > [this file]\n\
+- *\n\
++ * Automatically generated file; Do not edit.\n\
+  */\n\
+ \n\
+ #include <linux/types.h>\n\
+ \n\
+ u8 dfont_unicount[%d] = \n\
+-{\n\t", basename(base_tblname), fontlen);
++{\n\t", fontlen);
+ 
+   for ( i = 0 ; i < fontlen ; i++ )
+     {

device/community/linux-postmarketos-omap/0005-Add-TWL6030-power-button-support-to-twl-pwrbutton.patch

@@ -1,30 +1,3 @@
-diff --git a/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt b/Documentation/devicetree/bindings/input/twl-pwrbutton.txt
-similarity index 64%
-rename from Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt
-rename to Documentation/devicetree/bindings/input/twl-pwrbutton.txt
-index f5021214e..b49e2608f 100644
---- a/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt
-+++ b/Documentation/devicetree/bindings/input/twl-pwrbutton.txt
-@@ -1,6 +1,6 @@
--Texas Instruments TWL family (twl4030) pwrbutton module
-+Texas Instruments TWL family pwrbutton module
-
--This module is part of the TWL4030. For more details about the whole
-+This module is part of a TWL chip. For more details about the whole
- chip see Documentation/devicetree/bindings/mfd/ti,twl.yaml.
-
- This module provides a simple power button event via an Interrupt.
-@@ -8,8 +8,9 @@ This module provides a simple power button event via an Interrupt.
- Required properties:
- - compatible: should be one of the following
-    - "ti,twl4030-pwrbutton": For controllers compatible with twl4030
-+   - "ti,twl6030-pwrbutton": For controllers compatible with twl6030
- - interrupts: should be one of the following
--   - <8>: For controllers compatible with twl4030
-+   - <8>: For controllers compatible with the twl
- 
- Example:
- 
 diff --git a/arch/arm/boot/dts/ti/omap/twl6030.dtsi b/arch/arm/boot/dts/ti/omap/twl6030.dtsi
 index 9d588cfaa..ac033debf 100644
 --- a/arch/arm/boot/dts/ti/omap/twl6030.dtsi

device/community/linux-postmarketos-omap/0010-bq27xxx_battery-map-edv1-to-low-battery-capacity.patch

@@ -1,42 +0,0 @@
-From 350df21c4f01137e3d29f445e36aeb6c82b85e34 Mon Sep 17 00:00:00 2001
-From: "Sicelo A. Mhlongo" <absicsz@gmail.com>
-Date: Mon, 11 Sep 2023 10:34:54 +0200
-Subject: [PATCH 1/2] bq27xxx_battery: map edv1 to low battery capacity
-
-EDV1 is the most reliable indicator for battery low state on the N900/bq27200,
-and the driver already exposes it in the POWER_SUPPLY_PROP_CAPACITY_LEVEL (Low)
-and POWER_SUPPLY_PROP_HEALTH (Dead) properties. However, most userspace,
-including upower, does not use these properties for decision-making. Map EDV1
-state to very low battery capacity to force userspace to act on EDV1.
-
-Signed-off-by: Sicelo A. Mhlongo <absicsz@gmail.com>
----
- drivers/power/supply/bq27xxx_battery.c | 12 +++++++++++-
- 1 file changed, 11 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c
-index 4296600e8912..0789061ae9a0 100644
---- a/drivers/power/supply/bq27xxx_battery.c
-+++ b/drivers/power/supply/bq27xxx_battery.c
-@@ -1851,7 +1851,17 @@ static void bq27xxx_battery_update_unlocked(struct bq27xxx_device_info *di)
- 			cache.time_to_full = bq27xxx_battery_read_time(di, BQ27XXX_REG_TTF);
- 
- 		cache.charge_full = bq27xxx_battery_read_fcc(di);
--		cache.capacity = bq27xxx_battery_read_soc(di);
-+
-+		/* HACK: If EDV1 flag is set, force capacity to report 1%, even though
-+		 * SEDV1 actually represents about 6.25%, per datasheet. This is to ensure
-+		 * that userspace, such as upower, can readily react to the true battery low
-+		 * state (EDV1 set) whether or not the reported SoC value is reliable.
-+		 */
-+		if (cache.flags & BQ27000_FLAG_EDV1)
-+			cache.capacity = 1;
-+		else
-+			cache.capacity = bq27xxx_battery_read_soc(di);
-+
- 		if (di->regs[BQ27XXX_REG_AE] != INVALID_REG_ADDR)
- 			cache.energy = bq27xxx_battery_read_energy(di);
- 		di->cache.flags = cache.flags;
--- 
-2.40.1
-

device/community/linux-postmarketos-omap/0011-bq27xxx_battery-add-voltage-based-capacity-estimatio.patch

@@ -1,65 +0,0 @@
-From 456b5d133e026811fd735096ff3884823279879c Mon Sep 17 00:00:00 2001
-From: "Sicelo A. Mhlongo" <absicsz@gmail.com>
-Date: Mon, 11 Sep 2023 11:14:56 +0200
-Subject: [PATCH] bq27xxx_battery: add voltage-based capacity estimation
-
-Use battery voltage to approximate the battery capacity, if the fuel gauge does
-not have valid data.
-
-Signed-off-by: Sicelo A. Mhlongo <absicsz@gmail.com>
----
- drivers/power/supply/bq27xxx_battery.c | 28 ++++++++++++++++++++++++--
- 1 file changed, 26 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c
-index 0789061ae9a0..9476caed0ef4 100644
---- a/drivers/power/supply/bq27xxx_battery.c
-+++ b/drivers/power/supply/bq27xxx_battery.c
-@@ -1017,6 +1017,8 @@ static struct {
- 
- static DEFINE_MUTEX(bq27xxx_list_lock);
- static LIST_HEAD(bq27xxx_battery_devices);
-+static int bq27xxx_battery_voltage(struct bq27xxx_device_info *di,
-+				   union power_supply_propval *val);
- 
- #define BQ27XXX_MSLEEP(i) usleep_range((i)*1000, (i)*1000+500)
- 
-@@ -1857,11 +1859,33 @@ static void bq27xxx_battery_update_unlocked(struct bq27xxx_device_info *di)
- 		 * that userspace, such as upower, can readily react to the true battery low
- 		 * state (EDV1 set) whether or not the reported SoC value is reliable.
- 		 */
--		if (cache.flags & BQ27000_FLAG_EDV1)
-+		if (cache.flags & BQ27000_FLAG_EDV1) {
- 			cache.capacity = 1;
--		else
-+		} else {
- 			cache.capacity = bq27xxx_battery_read_soc(di);
- 
-+			/* Use voltage to estimate capacity if valid data is not available in the
-+			 * fuel gauge.
-+			 */
-+			if ((cache.capacity == 0) &&
-+			     bq27xxx_battery_capacity_inaccurate(di, cache.flags)) {
-+				union power_supply_propval bqval;
-+				bq27xxx_battery_voltage(di, &bqval);
-+				if (bqval.intval > 4000000)
-+					cache.capacity = 90;
-+				else if (bqval.intval > 3840000)
-+					cache.capacity = 80;
-+				else if (bqval.intval > 3680000)
-+					cache.capacity = 50;
-+				else if (bqval.intval > 3550000)
-+					cache.capacity = 30;
-+				else if (bqval.intval > 3450000)
-+					cache.capacity = 20;
-+				else
-+					cache.capacity = 10;
-+			}
-+		}
-+
- 		if (di->regs[BQ27XXX_REG_AE] != INVALID_REG_ADDR)
- 			cache.energy = bq27xxx_battery_read_energy(di);
- 		di->cache.flags = cache.flags;
--- 
-2.40.1
-

device/community/linux-postmarketos-omap/0012-ARM-dts-n900-set-charge-current-limit-to-950mA.patch

@@ -1,33 +0,0 @@
-From 5ecf87e2f723fddf7437427678156288537b3525 Mon Sep 17 00:00:00 2001
-From: Arthur Demchenkov <spinal.by@gmail.com>
-Date: Wed, 28 Feb 2024 10:20:56 +0200
-Subject: [PATCH] ARM: dts: n900: set charge current limit to 950mA
-
-The vendor kernel used 950mA as the default. The same value works fine on
-the mainline Linux kernel, and has been tested extensively under Maemo
-Leste [1] and postmarketOS, who have been using it for a number of years.
-
-[1] https://github.com/maemo-leste/n9xx-linux/commit/fbc4ce7a84e59215914a8981afe918002b191493
-
-Signed-off-by: Arthur Demchenkov <spinal.by@gmail.com>
-Signed-off-by: Sicelo A. Mhlongo <absicsz@gmail.com>
----
- arch/arm/boot/dts/ti/omap/omap3-n900.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/ti/omap/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts
-index d33485341251..07c5b963af78 100644
---- a/arch/arm/boot/dts/ti/omap/omap3-n900.dts
-+++ b/arch/arm/boot/dts/ti/omap/omap3-n900.dts
-@@ -754,7 +754,7 @@ bq24150a: bq24150a@6b {
- 		ti,current-limit = <100>;
- 		ti,weak-battery-voltage = <3400>;
- 		ti,battery-regulation-voltage = <4200>;
--		ti,charge-current = <650>;
-+		ti,charge-current = <950>;
- 		ti,termination-current = <100>;
- 		ti,resistor-sense = <68>;
- 
--- 
-2.43.0
-

device/community/linux-postmarketos-omap/APKBUILD

@@ -3,15 +3,14 @@
 # Kernel config based on: arch/arm/configs/omap2plus_defconfig
 
 pkgname=linux-postmarketos-omap
-pkgver=6.9.3
-pkgrel=2
+pkgver=6.10.6
+pkgrel=0
 pkgdesc="Mainline kernel fork for OMAP devices"
 arch="armv7"
 url="https://kernel.org/"
 license="GPL-2.0-only"
 options="!strip !check !tracedeps pmb:cross-native pmb:kconfigcheck-community"
-makedepends="bash bison findutils flex openssl-dev perl gmp-dev mpc1-dev mpfr-dev postmarketos-installkernel xz"
-
+makedepends="bash bison findutils flex linux-headers openssl-dev perl gmp-dev mpc1-dev mpfr-dev postmarketos-installkernel xz"
 _carch="arm"
 _flavor="postmarketos-omap"
 _config="config-$_flavor.armv7"
@@ -42,9 +41,6 @@ source="
 	0007-hsi-ssi_port-force-pio-path.patch
 	0008-n900-dts-volume-keys.patch
 	0009-ARM-dts-disable-twl-off-idle-configuration-for-N900.patch
-	0010-bq27xxx_battery-map-edv1-to-low-battery-capacity.patch
-	0011-bq27xxx_battery-add-voltage-based-capacity-estimatio.patch
-	0012-ARM-dts-n900-set-charge-current-limit-to-950mA.patch
 "
 builddir="$srcdir/linux-$_kernver"
 replaces="linux-samsung-espresso3g linux-nokia-n900"
@@ -74,18 +70,15 @@ package() {
 }
 
 sha512sums="
-119320627a73c260725a51ee4234942cc137aeb8b7c67428204ae14e3b518cf7b770e75a8dd0df7fa910333a64241146eb8f93463163f386dae8ddbd6943a631  linux-6.9.3.tar.xz
+991ec7c7d2d490cb90b182a29e892dae586918eee7f3ff4b6e26f4ff9b31b6d7a31cdc31d25ca12243ecab59787aad75f0056b2fbe6997d0dfd68c357e7703af  linux-6.10.6.tar.xz
 b0bcd5aa9db5479d6daa310a9e167fd3316d523b5077c6aa25547af0c39249a4f1f94afb7e64b6bd626f05c949dd8baa76b3b55e4e642df55de9ffe786284564  config-postmarketos-omap.armv7
 9a187d93885f07467ec67094621b2d762607d58622e67172bdfcd8ba5f3d6aab900ca5d233efd3d447540f9b906ba950083a35997c84b315801604e1cd5cddc3  0001-Add-TWL6032-dtsi.patch
 f7d1a87088c65278a114125e732d5bebebb560a6245afb34e003083d808ef3f8c5f49ff23131953508a6daae111ab6adfffdbcf56b79260a6d4115f859c7bb3a  0002-arm-dts-Add-common-dtsi-for-espresso.patch
 089ca0547997c7cd5d1b65924c134eb6b7703a7439729923d3639d125763412fa7e826d1cb839ac0b6cd22e614f69a3b52605a75b571e271c33f9a27ff6ac9c2  0003-arm-dts-Add-espresso7-support.patch
 97f6671bd6fa02d095b726793a3ae68a5b94b0a89719006121a6eaf1607c477f74446489a0f62250edc3c193945f571c92196c85ec8043ae18a141ea9adffd51  0004-arm-dts-Add-espresso10-support.patch
-fe9ce7ed5757a1e72663c15e80cef47531b80150e8c45fa94c03a291edc39a401c0678894c3f7afbe9b78b5cbe88529982bd6c90ab3f515c31199e6939aa3b96  0005-Add-TWL6030-power-button-support-to-twl-pwrbutton.patch
+8d14c1e7946cee7f7301a909f4e41ed9c909f0de84190006dfc370558bccaf2113a5f00a303a6d623ebd7064098300db9d89b64506a4abd65cadc79d2be997fd  0005-Add-TWL6030-power-button-support-to-twl-pwrbutton.patch
 1a68e3a32ae1e56d325c0f759ee66d64d14f46a5d52e75ae008dfddac335beb3aa7acaf62abb95b6d5ce1557f0cf9b4c31ab78e110af178db1ac963bb377dbf0  0006-iio-rescale-revert-logic.patch
 c3af9715b3559c2d593f4fcfa078730722c7deeec132c5b83e085ff4d9815d85ef349384097c580efe1bbc37c60f42e18ef559f0abccfe236080670e4403fa77  0007-hsi-ssi_port-force-pio-path.patch
 b98ce806b3d5a0122086e4c9670639174470ff6d29851c60258cc5d699ce9a479dbf4996b24299fc075d25e9fe8f6b1250fafdff742deea0ddeaf53d342a9d72  0008-n900-dts-volume-keys.patch
 66abb5548910ad369608b08200f5835d5a8526c04cc3617221ef546f3e3d22cd944db91dc6727a5c26a102b24d8ef1306ea01254c9c382759afced91b31747ef  0009-ARM-dts-disable-twl-off-idle-configuration-for-N900.patch
-6680b264db0c992826f9da0078256ba20ffae3de26a77978106b94499d96e72ed90d9a35bb42be38bae1e798e7ddf068e3c5e7fe63462b3bbad5031195622192  0010-bq27xxx_battery-map-edv1-to-low-battery-capacity.patch
-cd91f0bb59e466c517b498a549357325be884bb1884986e593fef905a6210872024e0cab179df03833dfc6e8d1221441fa384466ae8227d82f6e70b22fce655c  0011-bq27xxx_battery-add-voltage-based-capacity-estimatio.patch
-a11493d762b8f1ee90384e1d2baba7c6b7b37f4c11a8e6a876c1476de52b44a8f5a93db2bcd0fe68bb7e91dd54c76396b46727f8e94fc4aad1754feed3822061  0012-ARM-dts-n900-set-charge-current-limit-to-950mA.patch
 "

device/community/linux-postmarketos-qcom-sdm670/APKBUILD

@@ -5,14 +5,15 @@
 _flavor="postmarketos-qcom-sdm670"
 pkgname=linux-$_flavor
 pkgver=6.10.2
-pkgrel=0
+pkgrel=1
 pkgdesc="Mainline Kernel fork for SDM670 devices"
 arch="aarch64"
 _carch="arm64"
 url="https://gitlab.com/sdm670-mainline/linux"
 license="GPL-2.0-only"
 options="!strip !check !tracedeps
-	pmb:cross-native"
+	pmb:cross-native
+	pmb:kconfigcheck-community"
 makedepends="
 	bash
 	bison
@@ -66,5 +67,5 @@ package() {
 
 sha512sums="
 b992e72c8a8f2186088afb427acb8b79760ddb6350087abe15c0ac6064d10bd77adb2c3e260cf3f2014f93dd4b9fafd3f5a9805e9905cf75907e53a1f672dc36  linux-sdm670-v6.10.2.tar.gz
-aa96f401a997f7c2ec2cbc89425f1915254666303039f97250a00d19ff21b2a2057ea6fc79b2d09f88333f08bdda0c5467be54174f2233f55ea8530b0689cae7  config-postmarketos-qcom-sdm670.aarch64
+359464f0c844f86f5f14e15d86f99e340fec5d0694f26a0706e6c3c0f5afe1da39d159c9e813a96a9dfc38f838a4362533a9c0ace7909ffb818713f507043d63  config-postmarketos-qcom-sdm670.aarch64
 "

device/community/linux-postmarketos-qcom-sdm670/config-postmarketos-qcom-sdm670.aarch64

@@ -182,7 +182,7 @@ CONFIG_CGROUP_WRITEBACK=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_CFS_BANDWIDTH=y
-CONFIG_RT_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
 CONFIG_SCHED_MM_CID=y
 CONFIG_UCLAMP_TASK_GROUP=y
 CONFIG_CGROUP_PIDS=y

device/community/linux-postmarketos-qcom-sm6350/APKBUILD

@@ -2,7 +2,7 @@
 
 _flavor="postmarketos-qcom-sm6350"
 pkgname=linux-$_flavor
-pkgver=6.10.3
+pkgver=6.10.5
 pkgrel=0
 pkgdesc="Mainline Kernel fork for SM6350/SM7225 devices"
 arch="aarch64"
@@ -54,6 +54,6 @@ package() {
 }
 
 sha512sums="
-a67427982aa13e89c0daea0da9780ce348e8b81e698089e7dfdf3d0710232eb7ea56bf1259d2090f2989282d5d9c6eabc458ffccb9b0b2d865ed428dfc886b32  linux-v6.10.3-sm6350.tar.gz
-cdf07e9f12605a7728223e794556916e0c89b2e8d9782b764b397b87c8aa59d570ece44d48fab26c394f1d701838da0796e2ee5be62455d169fc4f07eaae5ba2  config-postmarketos-qcom-sm6350.aarch64
+5756a8fd466f5c34dcaa9818d274facbe0b0b541ce9d7997b95868b2e84f1491ce8bf7d2714206ad8378d560996b8a736bc3c8505ef8022371644866c841e2a1  linux-v6.10.5-sm6350.tar.gz
+bf691e18576c41193549eea07c9f663d4e1c2c1615de87a50e67bfb6d2cef5b7943ad0cb9b759f3a1d5dc9f27f30f2d33d0ffca2e8dcbc96fcfd6a7ba15e242e  config-postmarketos-qcom-sm6350.aarch64
 "

device/community/linux-postmarketos-qcom-sm6350/config-postmarketos-qcom-sm6350.aarch64

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 6.10.3 Kernel Configuration
+# Linux/arm64 6.10.5 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 14.2.0) 14.2.0"
 CONFIG_CC_IS_GCC=y
@@ -379,9 +379,7 @@ CONFIG_ARM64_ERRATUM_2645198=y
 CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
 CONFIG_ARM64_ERRATUM_2966298=y
 CONFIG_ARM64_ERRATUM_3117295=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS=y
 CONFIG_ARM64_ERRATUM_3194386=y
-CONFIG_ARM64_ERRATUM_3312417=y
 # CONFIG_CAVIUM_ERRATUM_22375 is not set
 CONFIG_CAVIUM_ERRATUM_23144=y
 # CONFIG_CAVIUM_ERRATUM_23154 is not set

device/community/soc-qcom-sdm845/APKBUILD

@@ -3,21 +3,24 @@
 pkgname=soc-qcom-sdm845
 pkgdesc="Common package for Qualcomm SDM845 devices"
 pkgver=22
-pkgrel=1
+pkgrel=3
 url="https://postmarketos.org"
 license="BSD-3-Clause"
 arch="aarch64"
 options="!check !archcheck !tracedeps"
 depends="
 	swclock-offset
-	kmod
 "
 replaces="upower"
 subpackages="
 	$pkgname-modem
+	$pkgname-modem-openrc:modem_openrc
 	$pkgname-nonfree-firmware:nonfree_firmware
+	$pkgname-nonfree-firmware-openrc:nonfree_firmware_openrc
 	$pkgname-pulseaudio
+	$pkgname-pulseaudio-openrc:pulseaudio_openrc
 	$pkgname-qbootctl
+	$pkgname-qbootctl-openrc:qbootctl_openrc
 	$pkgname-ucm
 	$pkgname-vulkan
 "
@@ -55,13 +58,17 @@ modem() {
 	pkgdesc="Modem services and configuration"
 	depends="
 		q6voiced
-		q6voiced-openrc
 		msm-modem-uim-selection
 		81voltd
 	"
 
+	mkdir -p "$subpkgdir"
+}
+
+modem_openrc() {
+	install_if="$pkgname-modem=$pkgver-r$pkgrel openrc"
+	depends="q6voiced-openrc"
 	install="$subpkgname.post-install $subpkgname.post-upgrade"
-	mkdir "$subpkgdir"
 
 	install -Dm644 "$srcdir"/modemmanager.conf \
 		"$subpkgdir"/etc/conf.d/modemmanager
@@ -71,15 +78,23 @@ nonfree_firmware() {
 	pkgdesc="Modem, WiFi and GPU Firmware"
 	depends="
 		pd-mapper
-		pd-mapper-openrc
 		tqftpserv
-		tqftpserv-openrc
 		msm-modem
 		bootmac
 		alsa-utils
 	"
 
+	mkdir "$subpkgdir"
+}
+
+nonfree_firmware_openrc() {
+	install_if="$pkgname-nonfree-firmware=$pkgver-r$pkgrel openrc"
+	depends="
+		pd-mapper-openrc
+		tqftpserv-openrc
+	"
 	install="$subpkgname.post-install $subpkgname.post-upgrade"
+
 	mkdir "$subpkgdir"
 }
 
@@ -95,7 +110,14 @@ ucm() {
 qbootctl() {
 	pkgdesc="Enable qbootctl mark-boot-successful service"
 	depends="qbootctl"
+
+	mkdir "$subpkgdir"
+}
+
+qbootctl_openrc() {
+	install_if="$pkgname-qbootctl=$pkgver-r$pkgrel openrc"
 	install="$subpkgname.post-install $subpkgname.post-upgrade"
+
 	mkdir "$subpkgdir"
 }
 
@@ -108,12 +130,15 @@ vulkan() {
 
 pulseaudio() {
 	install_if="$pkgname=$pkgver-r$pkgrel pulseaudio"
-	replaces="$pkgname" # To migrate from workaround being in main package
-	install="$subpkgname.post-install $subpkgname.post-upgrade"
 
 	# Call Audio idle suspend workaround code
 	install -Dm755 "$srcdir"/call_audio_idle_suspend_workaround.sh \
 		"$subpkgdir"/usr/sbin/call_audio_idle_suspend_workaround
+}
+
+pulseaudio_openrc() {
+	install_if="$pkgname-pulseaudio=$pkgver-r$pkgrel openrc"
+	install="$subpkgname.post-install $subpkgname.post-upgrade"
 
 	# Call Audio idle suspend workaround init script
 	install -Dm755 "$srcdir"/call_audio_idle_suspend_workaround.initd \

device/community/soc-qcom-sdm845/soc-qcom-sdm845-modem-openrc.post-upgrade

@@ -0,0 +1 @@
+soc-qcom-sdm845-modem-openrc.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-modem.post-upgrade

@@ -1 +0,0 @@
-soc-qcom-sdm845-modem.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-nonfree-firmware-openrc.post-upgrade

@@ -0,0 +1 @@
+soc-qcom-sdm845-nonfree-firmware-openrc.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-nonfree-firmware.post-upgrade

@@ -1 +0,0 @@
-soc-qcom-sdm845-nonfree-firmware.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-pulseaudio-openrc.post-upgrade

@@ -0,0 +1 @@
+soc-qcom-sdm845-pulseaudio-openrc.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-pulseaudio.post-upgrade

@@ -1 +0,0 @@
-soc-qcom-sdm845-pulseaudio.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-qbootctl-openrc.post-upgrade

@@ -0,0 +1 @@
+soc-qcom-sdm845-qbootctl-openrc.post-install

device/community/soc-qcom-sdm845/soc-qcom-sdm845-qbootctl.post-upgrade

@@ -1 +0,0 @@
-soc-qcom-sdm845-qbootctl.post-install

device/main/linux-purism-librem5/APKBUILD

@@ -4,7 +4,7 @@
 # Contributor: Clayton Craft <clayton@craftyguy.net>
 pkgname=linux-purism-librem5
 pkgver=6.6.40
-pkgrel=1
+pkgrel=2
 # NOTE: Don't forget to rebase the config! See prepare() for instructions.
 _purismrel=2
 # <kernel ver>.<purism kernel release>
@@ -90,5 +90,5 @@ package() {
 
 sha512sums="
 b16f6d040024d826d4ac7a33ad23137fafbf1ac7ac8adeef3fd80a80dc308b70cf572de6e4a451eb607b1d18ad58c03493108c7a1ff9b26fa2bd03a475002903  linux-purism-librem5-6.6.40pureos2.tar.gz
-2982f5950820153cef5167b2cfebff7310b682266fda67fa370cebb8b6a93877f331a0f0877b127fc5ad186a72c9e6ed8b181ceeb6eb9ce74a56a4e9e4805ad2  config-purism-librem5.aarch64
+8039685a22032bc5dcda9b2abfb16aac3bb5a5f416e66e39178a593dfef15a1526b3d513b3c4120332dc1b1b1f72e0a97f7303c495fe3a648067842b51911868  config-purism-librem5.aarch64
 "

device/main/linux-purism-librem5/config-purism-librem5.aarch64

@@ -2,9 +2,9 @@
 # Automatically generated file; DO NOT EDIT.
 # Linux/arm64 6.6.40 Kernel Configuration
 #
-CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 13.2.1_git20240309) 13.2.1 20240309"
+CONFIG_CC_VERSION_TEXT="aarch64-alpine-linux-musl-gcc (Alpine 14.2.0) 14.2.0"
 CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=130201
+CONFIG_GCC_VERSION=140200
 CONFIG_CLANG_VERSION=0
 CONFIG_AS_IS_GNU=y
 CONFIG_AS_VERSION=24200
@@ -13,7 +13,6 @@ CONFIG_LD_VERSION=24200
 CONFIG_LLD_VERSION=0
 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
 CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
-CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
 CONFIG_CC_HAS_ASM_INLINE=y
 CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
 CONFIG_PAHOLE_VERSION=0
@@ -4769,10 +4768,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
 # end of Console display driver support
 
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO is not set
 # end of Graphics support
 
 # CONFIG_DRM_ACCEL is not set

device/testing/device-amazon-tate/APKBUILD

@@ -0,0 +1,35 @@
+# Reference: <https://postmarketos.org/devicepkg>
+pkgname=device-amazon-tate
+pkgdesc="Amazon Kindle Fire HD (2nd Generation)"
+pkgver=1
+pkgrel=0
+url="https://postmarketos.org"
+license="MIT"
+arch="armv7"
+options="!check !archcheck"
+depends="
+	postmarketos-base
+	linux-amazon-tate
+	mkbootimg
+"
+makedepends="devicepkg-dev"
+source="
+	deviceinfo
+	initfs-hook.sh
+	amazon-omap-boot-hack.sh
+"
+
+build() {
+	devicepkg_build $startdir $pkgname
+}
+
+package() {
+	devicepkg_package $startdir $pkgname
+	install -Dm755 "$srcdir/amazon-omap-boot-hack.sh" "$pkgdir/usr/share/mkinitfs/amazon-omap-boot-hack.sh"
+}
+
+sha512sums="
+2e06c09046be664bbba5d55aafb06aceafbf41777bf116caa508d461190d546cc7ceae5160f0582dee20d88b5998837c00ffc3de928d1e5892bb32485523ce79  deviceinfo
+1aca985770246b9ca140996a498815b5c9ca3458a6cb84db85825344f01deda8b1de7c88e2e0c610df636ad2179faac7fd90d9992add51186a6449f2d43a3f71  initfs-hook.sh
+a5027ac9f113018d55e4c5fc065b0498d0a50df099a348fe38d6b841087aa285a8d67b400b9fe88007f41d0fd79c2fe69d62300af6963ecb40c5fb2353cbabf1  amazon-omap-boot-hack.sh
+"

device/testing/device-amazon-tate/amazon-omap-boot-hack.sh

@@ -0,0 +1,12 @@
+#!/bin/sh
+
+echo "==> Amending boot.img for Amazon signature verification exploit"
+BOWSER_HEADER_DATA='\x50\x03\x00\x00\x00\x25\xe4\x00'
+BOWSER_HEADER_SIZE=1024
+BOWSER_HEADER_OFFSET=52
+tempfile=$(mktemp)
+bootimgfile=$(echo "${1}" | sed 's/initramfs/boot.img/g')
+dd if=/dev/zero of="${tempfile}" bs=$BOWSER_HEADER_SIZE count=1
+printf "%b" $BOWSER_HEADER_DATA | dd of="${tempfile}" bs=$BOWSER_HEADER_OFFSET seek=1 conv=notrunc
+cat "${bootimgfile}" >> "${tempfile}"
+mv "${tempfile}" "${bootimgfile}"

device/testing/device-amazon-tate/deviceinfo

@@ -0,0 +1,39 @@
+# Reference: <https://postmarketos.org/deviceinfo>
+# Please use double quotes only. You can source this file in shell
+# scripts.
+
+deviceinfo_format_version="0"
+deviceinfo_name="Amazon Kindle Fire HD (2nd Generation)"
+deviceinfo_manufacturer="Amazon"
+deviceinfo_codename="amazon-tate"
+deviceinfo_year="2012"
+deviceinfo_arch="armv7"
+
+# Device related
+deviceinfo_gpu_accelerated="false"
+deviceinfo_chassis="tablet"
+deviceinfo_keyboard="false"
+deviceinfo_external_storage="false"
+deviceinfo_screen_width="800"
+deviceinfo_screen_height="1280"
+
+# Bootloader related
+deviceinfo_flash_method="fastboot"
+deviceinfo_kernel_cmdline="console=tty0 ignore_loglevel mem=1G init=/init"
+deviceinfo_generate_bootimg="true"
+deviceinfo_bootimg_qcdt="false"
+deviceinfo_bootimg_mtk_mkimage="false"
+deviceinfo_bootimg_dtb_second="false"
+deviceinfo_mkinitfs_postprocess="/usr/share/mkinitfs/amazon-omap-boot-hack.sh"
+deviceinfo_flash_offset_base="0x80000000"
+deviceinfo_flash_offset_kernel="0x00008000"
+deviceinfo_flash_offset_ramdisk="0x01000000"
+deviceinfo_flash_offset_second="0x00f00000"
+deviceinfo_flash_offset_tags="0x00000100"
+deviceinfo_flash_pagesize="2048"
+
+# Lab126, Inc.
+deviceinfo_usb_idVendor="0x1949"
+# Kindle
+deviceinfo_usb_idProduct="0x0007"
+

device/testing/device-amazon-tate/initfs-hook.sh

@@ -0,0 +1,5 @@
+#!/bin/sh
+
+# Turn overlay0 off and on again to remove bootloader screen
+echo 0 > /sys/devices/platform/omapdss/overlay0/enabled
+echo 1 > /sys/devices/platform/omapdss/overlay0/enabled

device/testing/device-asus-x00td/APKBUILD

@@ -2,7 +2,7 @@
 pkgname=device-asus-x00td
 pkgdesc="Asus ZenFone Max Pro M1"
 pkgver=1
-pkgrel=1
+pkgrel=2
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -32,7 +32,7 @@ kernel_downstream() {
 
 kernel_mainline() {
 	pkgdesc="Close to mainline; for kernel development only (most features aren't working)"
-	depends="linux-postmarketos-qcom-sdm660"
+	depends="linux-postmarketos-qcom-sdm660 soc-qcom-sdm660 soc-qcom-sdm660-rproc"
 	devicepkg_subpackage_kernel $startdir $pkgname $subpkgname
 }
 

device/testing/device-google-asurada/APKBUILD

@@ -2,8 +2,8 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-asurada
 pkgdesc="Google Asurada Chromebooks"
-pkgver=2
-pkgrel=1
+pkgver=3
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -35,6 +35,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-181faa71684361dbdcd49f2d16786ce8cd2366814f54a18c9e9caa989529ccc045713688d822a053959f88382a716622232276acf68d2f95597ac307ddf2240c  deviceinfo
+d497233fa521d67a04a87d6c1ca0c4360fc182856f9db1eff46f567127f258aa2516b1fbc4b0d1881f08204656b48b899becc7bdf6cbc6299dd6302505767495  deviceinfo
 d90b91bd2bb409941878ebadf8d28ef66406edb64cbcac99443c3e0c072801ba94ec9fa3b551f59b8a27a33c7a34f511604bd30328195fc261f927d87138801d  modules-initfs
 "

device/testing/device-google-asurada/deviceinfo

@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8192"
 # board here.
 deviceinfo_depthcharge_board="mt8192"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"

device/testing/device-google-cherry/APKBUILD

@@ -2,7 +2,7 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-cherry
 pkgdesc="Google Cherry Chromebooks"
-pkgver=2
+pkgver=3
 pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
@@ -35,6 +35,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-d69f5edb2dbc277561787306ea7fbb4cc4b1077a9385984e56bf38c24938630b17611fdb6e3c733b6a100b55256a266b60fba0adc0d952aaaaa2c2169d149007  deviceinfo
+6661b7c7a880dc3991921b1395ea48023a641b2d3f8e46d005b5778fed1bc5b5c0d55fa5d43499f00bb7453fde8d644ba3ae50d98de10f2daa62ad34bd1580c9  deviceinfo
 bb7f9a426bfa151c53089f07fd4e874b1fb69fd8180a584b4c9824e2d5ea1e7678602d74eb641b2640b692fec73b88acc78ca26ba9c9f3b8ac8366c6fb63dd5f  modules-initfs
 "

device/testing/device-google-cherry/deviceinfo

@@ -32,4 +32,5 @@ deviceinfo_cgpt_kpart_size="262144"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8195"
 # board here.
 deviceinfo_depthcharge_board="mt8195"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"