sony-ps4: new device

2024-10-02 20:57:05 +02:00
27 changed files with 18728 additions and 0 deletions
@@ -0,0 +1,38 @@
+pkgname=device-sony-ps4
+pkgdesc="Sony Playstation 4 Original"
+pkgver=1
+pkgrel=0
+url="https://postmarketos.org"
+license="MIT"
+arch="x86_64"
+options="!check !archcheck"
+depends="
+	linux-sony-ps4
+	postmarketos-base
+	grub-efi-x86
+	"
+makedepends="devicepkg-dev"
+source="
+	deviceinfo
+	modules-initfs
+	"
+subpackages="$pkgname-nonfree-firmware:nonfree_firmware"
+
+build() {
+	devicepkg_build $startdir $pkgname
+}
+
+package() {
+	devicepkg_package $startdir $pkgname
+}
+
+nonfree_firmware() {
+	pkgdesc="Wi-Fi and bluetooth firmware"
+	depends="linux-firmware-mrvl"
+	mkdir "$subpkgdir"
+}
+
+sha512sums="
+065faa7aed5acc1a8e15e1fe1e06929b57dc11030b7c842e7a46f7d4fae310ce3796a2d760a95222177c0d1d23f1e6cd982c3241a06e50c6d4961e69d3ce4450  deviceinfo
+24ed2457630757df9e69b3216b883c3032848b3cc692fd5cf0252baa6dc0dbea33e95b20767a9cb36e8461a8e79e65d50cc5ecd3a6801dc3e8e90951a34138aa  modules-initfs
+"
@@ -0,0 +1,24 @@
+# Reference: <https://postmarketos.org/deviceinfo>
+# Please use double quotes only. You can source this file in shell
+# scripts.
+
+deviceinfo_format_version="0"
+deviceinfo_name="Sony Playstation 4"
+deviceinfo_manufacturer="Sony"
+deviceinfo_codename="sony-ps4"
+deviceinfo_year="2013"
+deviceinfo_arch="x86_64"
+deviceinfo_gpu_accelerated="true"
+
+# Device related
+deviceinfo_chassis="desktop"
+deviceinfo_keyboard="false"
+deviceinfo_external_storage="true"
+deviceinfo_screen_width="1920"
+deviceinfo_screen_height="1080"
+deviceinfo_framebuffer_landscape="true"
+# Bootloader related
+deviceinfo_flash_method="none"
+deviceinfo_kernel_cmdline="panic=0 clocksource=tsc consoleblank=0 drm.debug=0 drm.edid_firmware=edid/my_edid.bin"
+deviceinfo_partition_type="gpt"
+deviceinfo_boot_filesystem="fat32"
@@ -0,0 +1 @@
+hid-steam
@@ -0,0 +1,37 @@
+From e9382715a310fc01a375e6e3eff7b185ce4277b4 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 14:01:45 +0100
+Subject: [PATCH 04/22] feat: temperature sensors
+
+---
+ drivers/hwmon/fam15h_power.c | 1 +
+ drivers/hwmon/k10temp.c      | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
+index 521534d5c1e5..5b84627c7942 100644
+--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
+@@ -486,6 +486,7 @@ static const struct pci_device_id fam15h_power_id_table[] = {
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
+	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M41H_F4) },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 3618a924e78e..478672b391cb 100644
+--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
+@@ -487,6 +487,7 @@ static const struct pci_device_id k10temp_id_table[] = {
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
+	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M41H_F3) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
+ 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+-- 
+2.45.1
+
@@ -0,0 +1,147 @@
+From 0d69fe3288f2c3444a25c72847a6d670ab07c77b Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 14:56:09 +0100
+Subject: [PATCH 05/22] feat: sdhci support
+
+---
+ drivers/mmc/host/sdhci-pci-core.c | 67 +++++++++++++++++++++++++++++++
+ drivers/mmc/host/sdhci-pci.h      |  2 +
+ 2 files changed, 69 insertions(+)
+
+diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
+index 8736e04fa73c..d50a3658820d 100644
+--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
+@@ -37,6 +37,10 @@
+ 
+ #include "cqhci.h"
+ 
+#ifdef CONFIG_X86_PS4
+#include <asm/ps4.h>
+#endif
+
+ #include "sdhci.h"
+ #include "sdhci-pci.h"
+ 
+@@ -319,6 +323,54 @@ static const struct sdhci_pci_fixes sdhci_intel_qrk = {
+ 	.quirks		= SDHCI_QUIRK_NO_HISPD_BIT,
+ };
+ 
+#ifdef CONFIG_X86_PS4
+static int aeolia_probe(struct sdhci_pci_chip *chip)
+{
+	chip->num_slots = 1;
+	chip->first_bar = 0;
+	if (apcie_status() == 0)
+		return -EPROBE_DEFER;
+
+	chip->pdev->class &= ~0x0000FF;
+	chip->pdev->class |= PCI_SDHCI_IFDMA;
+	return 0;
+}
+
+static int aeolia_probe_slot(struct sdhci_pci_slot *slot)
+{
+	int err = apcie_assign_irqs(slot->chip->pdev, 1);
+	if (err <= 0) {
+		dev_err(&slot->chip->pdev->dev, "failed to get IRQ: %d\n", err);
+		return -ENODEV;
+	}
+	slot->host->irq = slot->chip->pdev->irq;
+	return 0;
+}
+
+static void aeolia_remove_slot(struct sdhci_pci_slot *slot, int dead)
+{
+	apcie_free_irqs(slot->chip->pdev->irq, 1);
+}
+
+static int aeolia_enable_dma(struct sdhci_pci_slot *slot)
+{
+	if (pci_set_dma_mask(slot->chip->pdev, DMA_BIT_MASK(31))) {
+		return -EINVAL;
+	}
+	if (pci_set_consistent_dma_mask(slot->chip->pdev, DMA_BIT_MASK(31))) {
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static const struct sdhci_pci_fixes sdhci_aeolia = {
+	.probe		= aeolia_probe,
+	.probe_slot	= aeolia_probe_slot,
+	.remove_slot	= aeolia_remove_slot,
+	.enable_dma	= aeolia_enable_dma,
+};
+#endif
+
+ static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
+ {
+ 	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+@@ -1974,6 +2026,12 @@ static const struct pci_device_id pci_ids[] = {
+ 	SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
+ 	SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
+ 	SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
+	#ifdef CONFIG_X86_PS4
+	SDHCI_PCI_DEVICE(SONY, AEOLIA_SDHCI, aeolia),
+	SDHCI_PCI_DEVICE(SONY, BELIZE_SDHCI, aeolia),
+	// TODO (ps4patches): What is this doing in comments?
+	//SDHCI_PCI_DEVICE(SONY, BAIKAL_SDHCI, aeolia),
+	#endif
+ 	SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
+ 	SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
+ 	SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
+@@ -2008,6 +2066,10 @@ int sdhci_pci_enable_dma(struct sdhci_host *host)
+ 
+ 	pci_set_master(pdev);
+ 
+	if (slot->chip->fixes && slot->chip->fixes->enable_dma) {
+		return slot->chip->fixes->enable_dma(slot);
+	}
+
+ 	return 0;
+ }
+ 
+@@ -2361,6 +2423,7 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
+ 		chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
+ 	}
+ 	chip->num_slots = slots;
+	chip->first_bar = first_bar;
+ 	chip->pm_retune = true;
+ 	chip->rpm_retune = true;
+ 
+@@ -2375,7 +2438,11 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
+ 	slots = chip->num_slots;	/* Quirk may have changed this */
+ 
+ 	for (i = 0; i < slots; i++) {
+		#ifdef CONFIG_X86_PS4
+		slot = sdhci_pci_probe_slot(pdev, chip, chip->first_bar, i);
+		#else
+ 		slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
+		#endif
+ 		if (IS_ERR(slot)) {
+ 			for (i--; i >= 0; i--)
+ 				sdhci_pci_remove_slot(chip->slots[i]);
+diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
+index dcd99d5057ee..8caa7acbddb0 100644
+--- a/drivers/mmc/host/sdhci-pci.h
+++ b/drivers/mmc/host/sdhci-pci.h
+@@ -140,6 +140,7 @@ struct sdhci_pci_fixes {
+ 	int			(*probe_slot) (struct sdhci_pci_slot *);
+ 	int			(*add_host) (struct sdhci_pci_slot *);
+ 	void			(*remove_slot) (struct sdhci_pci_slot *, int);
+	int			(*enable_dma) (struct sdhci_pci_slot *);
+ 
+ #ifdef CONFIG_PM_SLEEP
+ 	int			(*suspend) (struct sdhci_pci_chip *);
+@@ -181,6 +182,7 @@ struct sdhci_pci_chip {
+ 	const struct sdhci_pci_fixes *fixes;
+ 
+ 	int			num_slots;	/* Slots on controller */
+	int			first_bar;	/* First valid BAR */
+ 	struct sdhci_pci_slot	*slots[MAX_SLOTS]; /* Pointers to host slots */
+ };
+ 
+-- 
+2.45.1
+
@@ -0,0 +1,323 @@
+From 905b33761e7344f07d4b2270896ebaa298d55047 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 15:29:54 +0100
+Subject: [PATCH 06/22] feat: ethernet support
+
+---
+ drivers/net/ethernet/marvell/sky2.c | 164 +++++++++++++++++++++++++---
+ drivers/net/ethernet/marvell/sky2.h |   3 +
+ 2 files changed, 150 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
+index e9fc74e54b22..66ee6f8ab1bd 100644
+--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
+@@ -38,6 +38,11 @@
+ 
+ #include <asm/irq.h>
+ 
+#ifdef CONFIG_X86_PS4
+#include <asm/ps4.h>
+#include "../../../ps4/aeolia.h"
+#endif
+
+ #include "sky2.h"
+ 
+ #define DRV_NAME		"sky2"
+@@ -134,6 +139,9 @@ static const struct pci_device_id sky2_id_table[] = {
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
+ 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
+	{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_GBE) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BELIZE_GBE) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BAIKAL_GBE) },
+ 	{ 0 }
+ };
+ 
+@@ -154,7 +162,7 @@ static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
+ 
+ 	gma_write16(hw, port, GM_SMI_DATA, val);
+ 	gma_write16(hw, port, GM_SMI_CTRL,
+-		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
+		    GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
+ 
+ 	for (i = 0; i < PHY_RETRIES; i++) {
+ 		u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
+@@ -179,7 +187,7 @@ static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
+ {
+ 	int i;
+ 
+-	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
+	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(hw->phy_addr)
+ 		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
+ 
+ 	for (i = 0; i < PHY_RETRIES; i++) {
+@@ -1375,7 +1383,7 @@ static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+ 
+ 	switch (cmd) {
+ 	case SIOCGMIIPHY:
+-		data->phy_id = PHY_ADDR_MARV;
+		data->phy_id = hw->phy_addr;
+ 
+ 		fallthrough;
+ 	case SIOCGMIIREG: {
+@@ -3234,6 +3242,24 @@ static void sky2_reset(struct sky2_hw *hw)
+ 	int i;
+ 	u32 hwe_mask = Y2_HWE_ALL_MASK;
+ 
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY &&
+	    pdev->device == PCI_DEVICE_ID_SONY_AEOLIA_GBE) {
+		u32 val1, val2;
+
+		sky2_write32(hw, 0x60, 0x32100);
+		sky2_write32(hw, 0x64, 6);
+		sky2_write32(hw, 0x68, 0x63b9c);
+		sky2_write32(hw, 0x6c, 0x300);
+		val1 = sky2_read32(hw, 0x158);
+		val2 = sky2_read32(hw, 0x160);
+		val1 &= ~0x33333333;
+		val2 &= ~0xCC00000;
+		sky2_write32(hw, 0x158, val1);
+		sky2_write32(hw, 0x160, val2);
+	}
+	#endif
+
+ 	/* disable ASF */
+ 	if (hw->chip_id == CHIP_ID_YUKON_EX
+ 	    || hw->chip_id == CHIP_ID_YUKON_SUPR) {
+@@ -3298,6 +3324,13 @@ static void sky2_reset(struct sky2_hw *hw)
+ 		sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
+ 	}
+ 
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY &&
+	    pdev->device == PCI_DEVICE_ID_SONY_AEOLIA_GBE) {
+		; /* Do not perform phy resets on aeolia, it will hang */
+	} else
+	#endif
+
+ 	if (hw->chip_id == CHIP_ID_YUKON_OPT ||
+ 	    hw->chip_id == CHIP_ID_YUKON_PRM ||
+ 	    hw->chip_id == CHIP_ID_YUKON_OP_2) {
+@@ -3582,7 +3615,7 @@ static int sky2_get_link_ksettings(struct net_device *dev,
+ 	u32 supported, advertising;
+ 
+ 	supported = sky2_supported_modes(hw);
+-	cmd->base.phy_address = PHY_ADDR_MARV;
+	cmd->base.phy_address = hw->phy_addr;
+ 	if (sky2_is_copper(hw)) {
+ 		cmd->base.port = PORT_TP;
+ 		cmd->base.speed = sky2->speed;
+@@ -4726,6 +4759,44 @@ static const struct net_device_ops sky2_netdev_ops[2] = {
+   },
+ };
+ 
+#ifdef CONFIG_X86_PS4
+/* NOTE: This region is no longer referenced by current ps4 x86 code. */
+/* However it still contains the mac address. */
+static void aeolia_get_mac_address(struct sky2_hw *hw, unsigned char *addr) {
+	u8 default_addr[ETH_ALEN] = { 0x52, 0x54, 0x00, 0xf0, 0xff, 0x0f };
+	unsigned int mem_devfn = PCI_DEVFN(PCI_SLOT(hw->pdev->devfn), AEOLIA_FUNC_ID_MEM);
+	struct pci_dev *mem_dev;
+	phys_addr_t bp_base;
+	void __iomem *bp;
+
+	memcpy(addr, default_addr, sizeof(default_addr));
+
+	mem_dev = pci_get_slot(hw->pdev->bus, mem_devfn);
+	if (!mem_dev) {
+		dev_err(&hw->pdev->dev, "sky2: could not get handle to mem device\n");
+		return;
+	}
+
+	bp_base = pci_resource_start(mem_dev, 5) + APCIE_SPM_BP_BASE;
+	if (!request_mem_region(bp_base, APCIE_SPM_BP_SIZE, "spm.bp")) {
+		dev_err(&hw->pdev->dev, "sky2: failed to request bootparam SPM region\n");
+		return;
+	}
+
+	bp = ioremap(bp_base, APCIE_SPM_BP_SIZE);
+	if (!bp) {
+		dev_err(&hw->pdev->dev, "sky2: failed to map bootparam portion of SPM\n");
+		goto release_bp;
+	}
+
+	memcpy_fromio(addr, bp, ETH_ALEN);
+
+	iounmap(bp);
+release_bp:
+	release_mem_region(bp_base, APCIE_SPM_BP_SIZE);
+}
+#endif
+
+ /* Initialize network device */
+ static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
+ 					   int highmem, int wol)
+@@ -4798,26 +4869,34 @@ static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
+ 	else
+ 		dev->max_mtu = ETH_JUMBO_MTU;
+ 
+-	/* try to get mac address in the following order:
+-	 * 1) from device tree data
+-	 * 2) from internal registers set by bootloader
+-	 */
+-	ret = of_get_mac_address(hw->pdev->dev.of_node, dev->dev_addr);
+-	if (ret)
+-		memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
+-			      ETH_ALEN);
+	#ifdef CONFIG_X86_PS4
+	if (hw->pdev->vendor == PCI_VENDOR_ID_SONY) {
+		aeolia_get_mac_address(hw, dev->dev_addr);
+	} else
+	#endif
+	{
+		/* try to get mac address in the following order:
+		 * 1) from device tree data
+	 	 * 2) from internal registers set by bootloader
+	 	 */
+		ret = of_get_mac_address(hw->pdev->dev.of_node, dev->dev_addr);
+		if (ret)
+			memcpy_fromio(dev->dev_addr,
+				      hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
+	}
+ 
+ 	/* if the address is invalid, use a random value */
+ 	if (!is_valid_ether_addr(dev->dev_addr)) {
+ 		struct sockaddr sa = { AF_UNSPEC };
+ 
+-		dev_warn(&hw->pdev->dev, "Invalid MAC address, defaulting to random\n");
+		dev_warn(&hw->pdev->dev,
+			 "Invalid MAC address, defaulting to random\n");
+ 		eth_hw_addr_random(dev);
+ 		memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
+ 		if (sky2_set_mac_address(dev, &sa))
+-			dev_warn(&hw->pdev->dev, "Failed to set MAC address.\n");
+			dev_warn(&hw->pdev->dev,
+				 "Failed to set MAC address.\n");
+ 	}
+-
+ 	return dev;
+ }
+ 
+@@ -4957,6 +5036,12 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 	u32 reg;
+ 	char buf1[16];
+ 
+	#ifdef CONFIG_X86_PS4
+	/* This will return negative on non-PS4 platforms */
+	if (apcie_status() == 0)
+		return -EPROBE_DEFER;
+	#endif
+
+ 	err = pci_enable_device(pdev);
+ 	if (err) {
+ 		dev_err(&pdev->dev, "cannot enable PCI device\n");
+@@ -4988,6 +5073,16 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 
+ 	pci_set_master(pdev);
+ 
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+		if (pci_set_dma_mask(pdev, DMA_BIT_MASK(31)) < 0 ||
+		    pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(31)) < 0) {
+			dev_err(&pdev->dev, "no usable DMA configuration\n");
+			goto err_out_free_regions;
+		}
+	} else
+	#endif
+
+ 	if (sizeof(dma_addr_t) > sizeof(u32) &&
+ 	    !(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))) {
+ 		using_dac = 1;
+@@ -5036,6 +5131,16 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 		goto err_out_free_hw;
+ 	}
+ 
+	hw->phy_addr = PHY_ADDR_MARV;
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY &&
+	    pdev->device == PCI_DEVICE_ID_SONY_AEOLIA_GBE) {
+		/* aeolia supports some sort of "l2 switch" */
+		/* it has normal phy at addr 1 with a possibly-active switch at addr 2 */
+		hw->phy_addr = 1;
+	}
+	#endif
+
+ 	err = sky2_init(hw);
+ 	if (err)
+ 		goto err_out_iounmap;
+@@ -5064,6 +5169,19 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 	if (disable_msi == -1)
+ 		disable_msi = !!dmi_check_system(msi_blacklist);
+ 
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY &&
+	    apcie_assign_irqs(pdev, 1) > 0) {
+		err = sky2_test_msi(hw);
+		if (err) {
+			apcie_free_irqs(pdev->irq, 1);
+			/* PS4 requires MSI, so if it fails, bail out. */
+			goto err_out_free_netdev;
+		}
+		hw->flags |= SKY2_HW_USE_AEOLIA_MSI;
+	} else
+	#endif
+
+ 	if (!disable_msi && pci_enable_msi(pdev) == 0) {
+ 		err = sky2_test_msi(hw);
+ 		if (err) {
+@@ -5120,8 +5238,14 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ err_out_unregister:
+ 	unregister_netdev(dev);
+ err_out_free_netdev:
+-	if (hw->flags & SKY2_HW_USE_MSI)
+-		pci_disable_msi(pdev);
+	#ifdef CONFIG_X86_PS4
+	if (hw->flags & SKY2_HW_USE_AEOLIA_MSI)
+		apcie_free_irqs(pdev->irq, 1);
+	else
+	#endif
+		if (hw->flags & SKY2_HW_USE_MSI)
+			pci_disable_msi(pdev);
+
+ 	free_netdev(dev);
+ err_out_free_pci:
+ 	dma_free_coherent(&pdev->dev,
+@@ -5168,6 +5292,12 @@ static void sky2_remove(struct pci_dev *pdev)
+ 		free_irq(pdev->irq, hw);
+ 	}
+ 
+	#ifdef CONFIG_X86_PS4
+	if (hw->flags & SKY2_HW_USE_AEOLIA_MSI)
+		apcie_free_irqs(pdev->irq, 1);
+	else
+	#endif
+
+ 	if (hw->flags & SKY2_HW_USE_MSI)
+ 		pci_disable_msi(pdev);
+ 	dma_free_coherent(&pdev->dev,
+diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
+index ddec1627f1a7..eeb3a5a8b029 100644
+--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
+@@ -2289,6 +2289,8 @@ struct sky2_hw {
+ #define SKY2_HW_RSS_CHKSUM	0x00000400	/* RSS requires chksum */
+ #define SKY2_HW_IRQ_SETUP	0x00000800
+ 
+#define SKY2_HW_USE_AEOLIA_MSI	0x00001000
+
+ 	u8	     	     chip_id;
+ 	u8		     chip_rev;
+ 	u8		     pmd_type;
+@@ -2303,6 +2305,7 @@ struct sky2_hw {
+ 	struct work_struct   restart_work;
+ 	wait_queue_head_t    msi_wait;
+ 
+	u8		     phy_addr;
+ 	char		     irq_name[];
+ };
+ 
+-- 
+2.45.1
+
@@ -0,0 +1,701 @@
+From 915809af6ee266c1c7792a0be01ae4da02d4766f Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 16:30:44 +0100
+Subject: [PATCH 07/22] feat: usb support
+
+---
+ drivers/usb/host/Kconfig       |   8 +
+ drivers/usb/host/Makefile      |   1 +
+ drivers/usb/host/xhci-aeolia.c | 585 +++++++++++++++++++++++++++++++++
+ drivers/usb/host/xhci-aeolia.h |  14 +
+ drivers/usb/host/xhci.c        |  30 +-
+ 5 files changed, 624 insertions(+), 14 deletions(-)
+ create mode 100644 drivers/usb/host/xhci-aeolia.c
+ create mode 100644 drivers/usb/host/xhci-aeolia.h
+
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index c4736d1d020c..92107bda6004 100644
+--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
+@@ -104,6 +104,14 @@ config USB_XHCI_TEGRA
+ 	  Say 'Y' to enable the support for the xHCI host controller
+ 	  found in NVIDIA Tegra124 and later SoCs.
+ 
+
+config USB_XHCI_AEOLIA
+	tristate "xHCI support for Sony PS4 (Aeolia)"
+	depends on X86_PS4
+	help
+	  Say 'Y' to enable the support for the xHCI host controller
+	  found in the Sony PlayStation 4.
+
+ endif # USB_XHCI_HCD
+ 
+ config USB_EHCI_BRCMSTB
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index 171de4df50bd..d0365fbf8b45 100644
+--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
+@@ -73,6 +73,7 @@ obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
+ obj-$(CONFIG_USB_XHCI_HISTB)	+= xhci-histb.o
+ obj-$(CONFIG_USB_XHCI_MTK)	+= xhci-mtk-hcd.o
+ obj-$(CONFIG_USB_XHCI_TEGRA)	+= xhci-tegra.o
+obj-$(CONFIG_USB_XHCI_AEOLIA)	+= xhci-aeolia.o
+ obj-$(CONFIG_USB_SL811_HCD)	+= sl811-hcd.o
+ obj-$(CONFIG_USB_SL811_CS)	+= sl811_cs.o
+ obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
+diff --git a/drivers/usb/host/xhci-aeolia.c b/drivers/usb/host/xhci-aeolia.c
+new file mode 100644
+index 000000000000..a9b345284495
+--- /dev/null
+++ b/drivers/usb/host/xhci-aeolia.c
+@@ -0,0 +1,585 @@
+/*
+ * xhci-aeoliat.c - xHCI host controller driver for Aeolia (Sony PS4)
+ *
+ * Borrows code from xhci-pci.c, hcd-pci.c, and xhci-plat.c.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/acpi.h>
+#include <asm/ps4.h>
+#include "xhci-aeolia.h"
+#include "../../ps4/aeolia.h"
+
+#include "xhci.h"
+
+static const char hcd_name[] = "xhci_aeolia";
+
+static struct hc_driver __read_mostly xhci_aeolia_hc_driver;
+
+#define NR_DEVICES 3
+
+struct aeolia_xhci {
+	// TODO (ps4patches): Belize, enable in ahci commit
+	// struct ata_host *host;
+	int nr_irqs;
+	struct usb_hcd *hcd[NR_DEVICES];
+};
+
+static int xhci_aeolia_setup(struct usb_hcd *hcd);
+
+static const struct xhci_driver_overrides xhci_aeolia_overrides __initconst = {
+	.extra_priv_size = sizeof(struct xhci_hcd),
+	.reset = xhci_aeolia_setup,
+};
+
+static void xhci_aeolia_quirks(struct device *dev, struct xhci_hcd *xhci)
+{
+	/*
+	 * Do not try to enable MSIs, we provide the MSIs ourselves
+	 * Do not touch DMA mask, we need a custom one
+	 */
+	xhci->quirks |= XHCI_PLAT | XHCI_PLAT_DMA;
+}
+
+/* called during probe() after chip reset completes */
+static int xhci_aeolia_setup(struct usb_hcd *hcd)
+{
+	return xhci_gen_setup(hcd, xhci_aeolia_quirks);
+}
+
+static int xhci_aeolia_probe_one(struct pci_dev *dev, int index)
+{
+	int retval;
+	struct aeolia_xhci *axhci = pci_get_drvdata(dev);
+	struct hc_driver *driver = &xhci_aeolia_hc_driver;
+	struct usb_hcd *hcd;
+	struct xhci_hcd *xhci;
+	int irq = (axhci->nr_irqs > 1) ? (dev->irq + index) : dev->irq;
+
+	// ok...adding this printk appears to have introduced a delay that fixed
+	// bringup of the middle host controller, so w/e for now...
+
+	printk("xhci_aeolia_probe_one %d, controller is %x\n", index, dev->device);
+
+	hcd = usb_create_hcd(driver, &dev->dev, pci_name(dev));
+	pci_set_drvdata(dev, axhci); /* usb_create_hcd clobbers this */
+	if (!hcd)
+		return -ENOMEM;
+
+	hcd->rsrc_start = pci_resource_start(dev, 2 * index);
+	hcd->rsrc_len = pci_resource_len(dev, 2 * index);
+
+	/*
+	 *  TODO (ps4patches): Belize, enable in ahci commit
+	if (!devm_request_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len,
+			driver->description)) {
+	*/
+
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+			     driver->description)) {
+		dev_dbg(&dev->dev, "controller already in use\n");
+		retval = -EBUSY;
+		goto put_hcd;
+	}
+	hcd->regs = pci_ioremap_bar(dev, 2 * index);
+	if (hcd->regs == NULL) {
+		dev_dbg(&dev->dev, "error mapping memory\n");
+		retval = -EFAULT;
+		goto release_mem_region;
+	}
+
+	device_wakeup_enable(hcd->self.controller);
+
+	xhci = hcd_to_xhci(hcd);
+	xhci->main_hcd = hcd;
+	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
+			pci_name(dev), hcd);
+	if (!xhci->shared_hcd) {
+		retval = -ENOMEM;
+		goto unmap_registers;
+	}
+
+	retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
+	if (retval)
+		goto put_usb3_hcd;
+
+	retval = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
+	if (retval)
+		goto dealloc_usb2_hcd;
+
+	axhci->hcd[index] = hcd;
+
+	return 0;
+
+dealloc_usb2_hcd:
+	usb_remove_hcd(hcd);
+put_usb3_hcd:
+	usb_put_hcd(xhci->shared_hcd);
+unmap_registers:
+	iounmap(hcd->regs);
+release_mem_region:
+	//
+	// devm_release_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+put_hcd:
+	usb_put_hcd(hcd);
+	dev_err(&dev->dev, "init %s(%d) fail, %d\n",
+			pci_name(dev), index, retval);
+	return retval;
+}
+
+static void xhci_aeolia_remove_one(struct pci_dev *dev, int index)
+{
+	struct aeolia_xhci *axhci = pci_get_drvdata(dev);
+	struct usb_hcd *hcd = axhci->hcd[index];
+	struct xhci_hcd *xhci;
+
+	if (!hcd)
+		return;
+	xhci = hcd_to_xhci(hcd);
+
+	usb_remove_hcd(xhci->shared_hcd);
+	usb_remove_hcd(hcd);
+	usb_put_hcd(xhci->shared_hcd);
+	iounmap(hcd->regs);
+	usb_put_hcd(hcd);
+	axhci->hcd[index] = NULL;
+}
+
+// TODO (ps4patches): Belize, enable in ahci commit
+//#define DRV_VERSION	"3.0"
+//#define DRV_NAME	"ahci"
+//static const struct ata_port_info ahci_port_info = {
+//	.flags		= AHCI_FLAG_COMMON,
+//	.pio_mask	= ATA_PIO4,
+//	.udma_mask	= ATA_UDMA6,
+//	.port_ops	= &ahci_ops,
+//};
+//
+//static struct scsi_host_template ahci_sht = {
+//	AHCI_SHT(DRV_NAME),
+//};
+//
+//static bool bus_master;
+//static int ahci_init_one(struct pci_dev *pdev)
+//{
+//	struct f_resource* r_mem;
+//	struct ahci_controller* ctlr;
+//	struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+//	struct ata_port_info pi = ahci_port_info;
+//	const struct ata_port_info *ppi[] = { &pi, NULL };
+//	struct ahci_host_priv *hpriv;
+//      struct ata_host *host;
+//	int n_ports, i, rc;
+//	int ahci_pci_bar = 2;
+//	resource_size_t		rsrc_start;
+//	resource_size_t		rsrc_len;
+//
+//	VPRINTK("ENTER\n");
+//
+//	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+//
+//	ata_print_version_once(&pdev->dev, DRV_VERSION);
+//
+//	/*
+//	rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
+//	if (rc == -EBUSY)
+//		pcim_pin_device(pdev);
+//	if (rc)
+//		return rc;
+//	*/
+//
+//	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
+//	//hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+//	if (!hpriv)
+//		return -ENOMEM;
+//	hpriv->flags |= (unsigned long)pi.private_data;
+//
+//	//hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
+//	rsrc_start = pci_resource_start(pdev, ahci_pci_bar);
+//	rsrc_len = pci_resource_len(pdev, ahci_pci_bar);
+//	//if (!request_mem_region(rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+//	if (!devm_request_mem_region(&pdev->dev, rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+//		dev_dbg(&pdev->dev, "controller already in use\n");
+//		rc = -EBUSY;
+//		goto put_hpriv;
+//	}
+//
+//
+//	hpriv->mmio = pci_ioremap_bar(pdev, ahci_pci_bar);
+//	if (hpriv->mmio == NULL) {
+//		dev_dbg(&pdev->dev, "error mapping memory\n");
+//		rc = -EFAULT;
+//		goto release_mem_region;
+//	}
+//
+//	r_mem = kzalloc(sizeof(*r_mem), GFP_KERNEL);
+//	if (r_mem) {
+//		r_mem->r_bustag = 1;//mem
+//		r_mem->r_bushandle = hpriv->mmio;
+//
+//		ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
+//		if (ctlr) {
+//			ctlr->r_mem = r_mem;
+//			ctlr->dev_id = 0; //or 0x90ca104d;
+//			ctlr->trace_len = 6;
+//			bpcie_sata_phy_init(&pdev->dev, ctlr);
+//			kfree(ctlr);
+//		}
+//		kfree(r_mem);
+//	}
+//	device_wakeup_enable(&pdev->dev);
+//
+//	/* save initial config */
+//	ahci_save_initial_config(&pdev->dev, hpriv);
+//
+//	/* prepare host */
+//	if (hpriv->cap & HOST_CAP_NCQ) {
+//		pi.flags |= ATA_FLAG_NCQ;
+//		/*
+//		 * Auto-activate optimization is supposed to be
+//		 * supported on all AHCI controllers indicating NCQ
+//		 * capability, but it seems to be broken on some
+//		 * chipsets including NVIDIAs.
+//		 */
+//		if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
+//			pi.flags |= ATA_FLAG_FPDMA_AA;
+//
+//		/*
+//		 * All AHCI controllers should be forward-compatible
+//		 * with the new auxiliary field. This code should be
+//		 * conditionalized if any buggy AHCI controllers are
+//		 * encountered.
+//		 */
+//		pi.flags |= ATA_FLAG_FPDMA_AUX;
+//	}
+//
+//	if (hpriv->cap & HOST_CAP_PMP)
+//		pi.flags |= ATA_FLAG_PMP;
+//
+//	ahci_set_em_messages(hpriv, &pi);
+//
+//	/* CAP.NP sometimes indicate the index of the last enabled
+//	 * port, at other times, that of the last possible port, so
+//	 * determining the maximum port number requires looking at
+//	 * both CAP.NP and port_map.
+//	 */
+//	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+//
+//	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
+//	if (!host) {
+//		rc = -ENOMEM;
+//		goto unmap_registers;
+//	}
+//	axhci->host = host;
+//	pci_set_drvdata(pdev, axhci);
+//
+//	host->private_data = hpriv;
+//
+//	{
+//		int index = 1;
+//		int irq = (axhci->nr_irqs > 1) ? (pdev->irq + index) : pdev->irq;
+//		hpriv->irq = irq;
+//	}
+//
+//	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+//		host->flags |= ATA_HOST_PARALLEL_SCAN;
+//	else
+//		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
+//
+//	if (pi.flags & ATA_FLAG_EM)
+//		ahci_reset_em(host);
+//
+//	for (i = 0; i < host->n_ports; i++) {
+//		struct ata_port *ap = host->ports[i];
+//
+//		ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
+//		ata_port_pbar_desc(ap, ahci_pci_bar,
+//				   0x100 + ap->port_no * 0x80, "port");
+//
+//		/* set enclosure management message type */
+//		if (ap->flags & ATA_FLAG_EM)
+//			ap->em_message_type = hpriv->em_msg_type;
+//
+//
+//		/* disabled/not-implemented port */
+//		if (!(hpriv->port_map & (1 << i)))
+//			ap->ops = &ata_dummy_port_ops;
+//	}
+//
+//	rc = ahci_reset_controller(host);
+//	dev_dbg(&pdev->dev, "ahci_reset_controller returned %d\n", rc);
+//	if (rc)
+//		goto release_host;
+//
+//	ahci_init_controller(host);
+//	ahci_print_info(host, "ATA");
+//
+//	if (!bus_master) {
+//		pci_set_master(pdev);
+//		bus_master = true;
+//	}
+//
+//	rc = ahci_host_activate(host, &ahci_sht);
+//	dev_dbg(&pdev->dev, "ahci_host_activate returned %d\n", rc);
+//	if (rc) {
+//		goto host_deactivate;
+//	}
+//
+//	pm_runtime_put_noidle(&pdev->dev);
+//	return 0;
+//
+//	host_deactivate:
+//	release_host:
+//	unmap_registers:
+//		iounmap(hpriv->mmio);
+//	release_mem_region:
+//
+//		release_mem_region(rsrc_start, rsrc_len);
+//
+//		// TODO (ps4patches): Belize, enable in ahci commit
+//		//devm_release_mem_region(&pdev->dev, rsrc_start, rsrc_len);
+//	put_hpriv:
+//		//kfree(hpriv);
+//		devm_kfree(&pdev->dev, hpriv);
+//		dev_err(&pdev->dev, "init %s fail, %d\n",
+//				pci_name(pdev), rc);
+//	return rc;
+//}
+//
+//static void ahci_remove_one(struct pci_dev *pdev)
+//{
+//	pm_runtime_get_noresume(&pdev->dev);
+//
+//	struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+//	if (axhci && axhci->host) {
+//		ata_host_detach(axhci->host);
+//		struct ahci_host_priv *hpriv = axhci->host->private_data;
+//		if (hpriv) {
+//			iounmap(hpriv->mmio);
+//		}
+//		axhci->host = NULL;
+//	}
+//}
+
+static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+	int idx;
+	int retval;
+	struct aeolia_xhci *axhci;
+
+	if (apcie_status() == 0)
+		return -EPROBE_DEFER;
+
+	if (pci_enable_device(dev) < 0)
+		return -ENODEV;
+
+	axhci = kzalloc(sizeof(*axhci), GFP_KERNEL);
+	// TODO (ps4patches): Belize, enable in ahci commit
+	// axhci = devm_kzalloc(&dev->dev, sizeof(*axhci), GFP_KERNEL);
+	if (!axhci) {
+		retval = -ENOMEM;
+		goto disable_device;
+	}
+	pci_set_drvdata(dev, axhci);
+
+	axhci->nr_irqs = retval = apcie_assign_irqs(dev, NR_DEVICES);
+	if (retval < 0) {
+		goto free_axhci;
+	}
+
+	// TODO (ps4patches): Belize, disable in ahci commit
+	pci_set_master(dev);
+
+	if (pci_set_dma_mask(dev, DMA_BIT_MASK(31)) ||
+		pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(31))) {
+		return -ENODEV;
+	}
+
+	// TODO (ps4patches): Belize, enable in ahci commit
+//	retval = ahci_init_one(dev);
+//	dev_dbg(&dev->dev, "ahci_init_one returned %d", retval);
+//	if (!bus_master) {
+//		pci_set_master(dev);
+//		bus_master = true;
+//	}
+
+	for (idx = 0; idx < NR_DEVICES; idx++) {
+ 		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1){ //this is for Belize and Baikal
+			continue;
+		}
+		retval = xhci_aeolia_probe_one(dev, idx);
+		if (retval)
+			goto remove_hcds;
+	}
+
+	return 0;
+
+remove_hcds:
+	while (idx--)
+		xhci_aeolia_remove_one(dev, idx);
+	apcie_free_irqs(dev->irq, axhci->nr_irqs);
+free_axhci:
+	kfree(axhci);
+
+	// TODO (ps4patches): Belize, disable in ahci commit
+	// devm_kfree(&dev->dev, axhci);
+	// pci_set_drvdata(dev, NULL);
+disable_device:
+	pci_disable_device(dev);
+	return retval;
+}
+
+static void xhci_aeolia_remove(struct pci_dev *dev)
+{
+	int idx;
+	struct aeolia_xhci *axhci = pci_get_drvdata(dev);
+	if (!axhci)
+		return;
+
+	for (idx = 0; idx < NR_DEVICES; idx++) {
+		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+			if(idx != 1)
+				xhci_aeolia_remove_one(dev, idx);
+			// TODO (ps4patches): Belize, enable in ahci commit
+			// else
+			//	ahci_remove_one(dev);
+		}
+		else
+			xhci_aeolia_remove_one(dev, idx);
+	}
+
+	apcie_free_irqs(dev->irq, axhci->nr_irqs);
+
+	// TODO (ps4patches): Belize, remove in ahci commit
+	kfree(axhci);
+
+	pci_disable_device(dev);
+}
+
+// TODO (ps4patches): Belize, enable in ahci commit
+//static void xhci_hcd_pci_shutdown(struct pci_dev *dev){
+//	struct aeolia_xhci *axhci;
+//	struct usb_hcd		*hcd;
+//	int idx;
+//
+//	axhci = pci_get_drvdata(dev);
+//	if (!axhci)
+//		return;
+//
+//	for (idx = 0; idx < NR_DEVICES; idx++) {
+//		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+//			if(idx != 1) {
+//				hcd = axhci->hcd[idx];
+//				if (hcd) {
+//					if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && hcd->driver->shutdown) {
+//						hcd->driver->shutdown(hcd);
+//						if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
+//							free_irq(hcd->irq, hcd);
+//					}
+//				}
+//			}
+//		}
+//	}
+//}
+
+
+static const struct pci_device_id pci_ids[] = {
+		{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_XHCI) },
+		{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BELIZE_XHCI) },
+		{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BAIKAL_XHCI) },
+	{ /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+#ifdef CONFIG_PM_SLEEP
+static int xhci_aeolia_suspend(struct device *dev)
+{
+	int idx;
+	struct aeolia_xhci *axhci = dev_get_drvdata(dev);
+	struct xhci_hcd	*xhci;
+	int retval;
+	struct pci_dev		*pdev = to_pci_dev(dev);
+
+	for (idx = 0; idx < NR_DEVICES; idx++) {
+		if(pdev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1)
+			continue;
+		xhci = hcd_to_xhci(axhci->hcd[idx]);
+		retval = xhci_suspend(xhci, device_may_wakeup(dev));
+		if (retval < 0)
+			goto resume;
+	}
+	return 0;
+
+resume:
+	while (idx--) {
+		xhci = hcd_to_xhci(axhci->hcd[idx]);
+		xhci_resume(xhci, 0);
+	}
+	return retval;
+}
+
+static int xhci_aeolia_resume(struct device *dev)
+{
+	int idx;
+	struct aeolia_xhci *axhci = dev_get_drvdata(dev);
+	struct xhci_hcd	*xhci;
+	int retval;
+	struct pci_dev		*pdev = to_pci_dev(dev);
+
+	for (idx = 0; idx < NR_DEVICES; idx++) {
+ 		if(pdev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1)
+			continue;
+		xhci = hcd_to_xhci(axhci->hcd[idx]);
+		retval = xhci_resume(xhci, 0);
+		if (retval < 0)
+			return retval;
+	}
+	return 0;
+}
+
+static const struct dev_pm_ops xhci_aeolia_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(xhci_aeolia_suspend, xhci_aeolia_resume)
+};
+#endif
+
+/* pci driver glue; this is a "new style" PCI driver module */
+static struct pci_driver xhci_aeolia_driver = {
+	.name =		"xhci_aeolia",
+	.id_table =	pci_ids,
+
+	.probe =	xhci_aeolia_probe,
+	.remove =	xhci_aeolia_remove,
+	/* suspend and resume implemented later */
+
+	.shutdown = usb_hcd_pci_shutdown,
+	// TODO (ps4patches): Belize, enable in ahci commit
+	//.shutdown = 	xhci_hcd_pci_shutdown,
+#ifdef CONFIG_PM_SLEEP
+	.driver = {
+		.pm = &xhci_aeolia_pm_ops
+	},
+#endif
+};
+
+static int __init xhci_aeolia_init(void)
+{
+	xhci_init_driver(&xhci_aeolia_hc_driver, &xhci_aeolia_overrides);
+	return pci_register_driver(&xhci_aeolia_driver);
+}
+module_init(xhci_aeolia_init);
+
+static void __exit xhci_aeolia_exit(void)
+{
+	pci_unregister_driver(&xhci_aeolia_driver);
+}
+module_exit(xhci_aeolia_exit);
+
+MODULE_DESCRIPTION("xHCI Aeolia Host Controller Driver");
+MODULE_LICENSE("GPL");
+diff --git a/drivers/usb/host/xhci-aeolia.h b/drivers/usb/host/xhci-aeolia.h
+new file mode 100644
+index 000000000000..2b711d6a92ca
+--- /dev/null
+++ b/drivers/usb/host/xhci-aeolia.h
+@@ -0,0 +1,14 @@
+/*
+ * xhci-aeolia.h
+ *
+ *  Created on: 31 Oct 2019
+ *      Author: visicva
+ */
+
+#ifndef DRIVERS_USB_HOST_XHCI_AEOLIA_H_
+#define DRIVERS_USB_HOST_XHCI_AEOLIA_H_
+
+#include "../../ata/ahci.h"
+#include <linux/irqdomain.h>
+
+#endif /* DRIVERS_USB_HOST_XHCI_AEOLIA_H_ */
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 1fd2f6a850eb..1c8fb48c7095 100644
+--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
+@@ -5373,20 +5373,22 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 
+ 	/* Set dma_mask and coherent_dma_mask to 64-bits,
+ 	 * if xHC supports 64-bit addressing */
+-	if (HCC_64BIT_ADDR(xhci->hcc_params) &&
+-			!dma_set_mask(dev, DMA_BIT_MASK(64))) {
+-		xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+-		dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
+-	} else {
+-		/*
+-		 * This is to avoid error in cases where a 32-bit USB
+-		 * controller is used on a 64-bit capable system.
+-		 */
+-		retval = dma_set_mask(dev, DMA_BIT_MASK(32));
+-		if (retval)
+-			return retval;
+-		xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
+-		dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+	if (!(xhci->quirks & XHCI_PLAT_DMA)) {
+		if (HCC_64BIT_ADDR(xhci->hcc_params) &&
+		    !dma_set_mask(dev, DMA_BIT_MASK(64))) {
+			xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+			dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
+		} else {
+			/*
+		 	 * This is to avoid error in cases where a 32-bit USB
+		 	 * controller is used on a 64-bit capable system.
+		 	 */
+			retval = dma_set_mask(dev, DMA_BIT_MASK(32));
+			if (retval)
+				return retval;
+			xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
+			dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+		}
+ 	}
+ 
+ 	xhci_dbg(xhci, "Calling HCD init\n");
+-- 
+2.45.1
+
@@ -0,0 +1,158 @@
+From 0bd681355cbd557d93a6cc62e0b816ed661095c9 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Tue, 21 Dec 2021 19:22:42 +0100
+Subject: [PATCH 09/22] feat: trying to modernize ps4-apcie so it works with
+ kernel 5.15
+
+---
+ arch/x86/include/asm/irqdomain.h |  1 +
+ arch/x86/kernel/apic/vector.c    | 11 ++++++++-
+ drivers/iommu/amd/iommu.c        |  2 ++
+ drivers/pci/probe.c              |  6 +++++
+ drivers/ps4/ps4-apcie.c          | 40 ++++++++++++++++++++++++--------
+ 5 files changed, 49 insertions(+), 11 deletions(-)
+
+diff --git a/arch/x86/include/asm/irqdomain.h b/arch/x86/include/asm/irqdomain.h
+index 125c23b7bad3..2f8410292efc 100644
+--- a/arch/x86/include/asm/irqdomain.h
+++ b/arch/x86/include/asm/irqdomain.h
+@@ -14,6 +14,7 @@ enum {
+ 
+ extern int x86_fwspec_is_ioapic(struct irq_fwspec *fwspec);
+ extern int x86_fwspec_is_hpet(struct irq_fwspec *fwspec);
+extern int x86_fwspec_is_aeolia(struct irq_fwspec *fwspec);
+ 
+ extern struct irq_domain *x86_vector_domain;
+ 
+diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
+index c132daabe615..af7339aaa843 100644
+--- a/arch/x86/kernel/apic/vector.c
+++ b/arch/x86/kernel/apic/vector.c
+@@ -676,6 +676,15 @@ int x86_fwspec_is_hpet(struct irq_fwspec *fwspec)
+ 	return 0;
+ }
+ 
+int x86_fwspec_is_aeolia(struct irq_fwspec *fwspec)
+{
+	if (is_fwnode_irqchip(fwspec->fwnode)) {
+		const char *fwname = fwnode_get_name(fwspec->fwnode);
+		return fwname && !strncmp(fwname, "Aeolia-MSI", 10);
+	}
+	return 0;
+}
+
+ static int x86_vector_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ 			     enum irq_domain_bus_token bus_token)
+ {
+@@ -687,7 +696,7 @@ static int x86_vector_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ 	if (apic->apic_id_valid(32768))
+ 		return 0;
+ 
+-	return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec);
+	return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec) || x86_fwspec_is_aeolia(fwspec);
+ }
+ 
+ static const struct irq_domain_ops x86_vector_domain_ops = {
+diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
+index 5ceaaabb4f9d..f20dc0c7b78f 100644
+--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
+@@ -3294,6 +3294,8 @@ static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ 		devid = get_ioapic_devid(fwspec->param[0]);
+ 	else if (x86_fwspec_is_hpet(fwspec))
+ 		devid = get_hpet_devid(fwspec->param[0]);
+	else if(x86_fwspec_is_aeolia(fwspec))
+		devid = fwspec->param[0];
+ 
+ 	if (devid < 0)
+ 		return 0;
+diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
+index 5fe5e84fab40..288b49cc49a5 100644
+--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
+@@ -2638,6 +2638,12 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
+ 		nr++;
+ 
+ 	for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
+		if (PCI_SLOT(devfn) != AEOLIA_SLOT_NUM &&
+		    pci_bus_read_dev_vendor_id(bus, devfn + fn, &l, 60*1000) &&
+		    (l & 0xffff) == PCI_VENDOR_ID_SONY) {
+			continue;
+		}
+
+ 		dev = pci_scan_single_device(bus, devfn + fn);
+ 		if (dev) {
+ 			if (!pci_dev_is_added(dev))
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index d5e87d1ee74e..d9c36f7715bb 100644
+--- a/drivers/ps4/ps4-apcie.c
+++ b/drivers/ps4/ps4-apcie.c
+@@ -219,28 +219,47 @@ static struct msi_domain_info apcie_msi_domain_info = {
+ 
+ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ {
+-	struct irq_domain *domain;
+	struct msi_domain_info *domain_info;
+	struct irq_domain *domain, *parent;
+ 	struct fwnode_handle *fn;
+	struct irq_fwspec fwspec;
+ 
+ 	sc_dbg("apcie_create_irq_domain\n");
+ 	if (x86_vector_domain == NULL)
+ 		return NULL;
+ 
+-	apcie_msi_domain_info.chip_data = (void *)sc;
+-	apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
+-	apcie_msi_controller.name = "IR-Aeolia-MSI";
+	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
+	if (!domain_info)
+		return NULL;
+
+	*domain_info = apcie_msi_domain_info;
+	domain_info->chip_data = (void *)sc;
+ 
+-	fn = irq_domain_alloc_named_fwnode(apcie_msi_controller.name);
+-	if (!fn)
+	fn = irq_domain_alloc_named_id_fwnode(apcie_msi_controller.name, pci_dev_id(sc->pdev));
+	if (!fn) {
+		kfree(domain_info);
+ 		return NULL;
+-	domain = pci_msi_create_irq_domain(fn, &apcie_msi_domain_info,
+-				      x86_vector_domain);
+	}
+
+	fwspec.fwnode = fn;
+	fwspec.param_count = 1;
+
+	// It should be correct to put the pci device id in here
+	fwspec.param[0] = pci_dev_id(sc->pdev);
+ 
+	parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
+	if (!parent) {
+		parent = x86_vector_domain;
+	} else {
+		apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
+		apcie_msi_controller.name = "IR-Aeolia-MSI";
+	}
+
+	domain = msi_create_irq_domain(fn, domain_info, parent);
+ 	if (!domain) {
+ 		irq_domain_free_fwnode(fn);
+		kfree(domain_info);
+ 		pr_warn("Failed to initialize IR-Aeolia-MSI irqdomain.\n");
+-	} else {
+-		domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
+ 	}
+ 
+ 	return domain;
+@@ -283,6 +302,7 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ 	info.type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
+ 	/* IRQs "come from" function 4 as far as the IOMMU/system see */
+ 	//info.msi_dev = sc->pdev;
+	info.desc = alloc_msi_entry(&dev->dev, nvec, NULL);
+ 	/* Our hwirq number is function << 8 plus subfunction.
+ 	 * Subfunction is usually 0 and implicitly increments per hwirq,
+ 	 * but can also be 0xff to indicate that this is a shared IRQ. */
+-- 
+2.45.1
+
@@ -0,0 +1,680 @@
+From 92a4a84d51795f0a765a0dc6b3db08ca60b74805 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Fri, 24 Dec 2021 22:40:25 +0100
+Subject: [PATCH 10/22] feat: working state, broken gpu
+
+---
+ drivers/ata/ahci.c                    | 289 ++++++++++++++++++++++++++
+ drivers/ata/ahci.h                    |  28 +++
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c |   6 +
+ drivers/iommu/amd/iommu.c             |   1 +
+ drivers/ps4/aeolia.h                  |   8 +-
+ drivers/ps4/ps4-apcie.c               |  95 ++++++---
+ 6 files changed, 392 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index 149ee16fd022..5ba41c18b295 100644
+--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
+@@ -34,6 +34,10 @@
+ #include <linux/io-64-nonatomic-lo-hi.h>
+ #include "ahci.h"
+ 
+#ifdef CONFIG_X86_PS4
+#include <asm/ps4.h>
+#endif
+
+ #define DRV_NAME	"ahci"
+ #define DRV_VERSION	"3.0"
+ 
+@@ -605,6 +609,11 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ 	/* Enmotus */
+ 	{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
+ 
+	/* Sony (PS4) */
+	{ PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_AEOLIA_AHCI), board_ahci },
+	{ PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_BELIZE_AHCI), board_ahci },
+	{ PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_BAIKAL_AHCI), board_ahci },
+
+ 	/* Loongson */
+ 	{ PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
+ 
+@@ -954,6 +963,23 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
+ 	if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
+ 		return 0;
+ 
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+		rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(31));
+		if (rc) {
+			dev_err(&pdev->dev, "31-bit DMA enable failed\n");
+			return rc;
+		}
+		rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31));
+		if (rc) {
+			dev_err(&pdev->dev,
+				"31-bit consistent DMA enable failed\n");
+			return rc;
+		}
+		return 0;
+	}
+	#endif
+
+ 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
+ 	if (rc)
+ 		dev_err(&pdev->dev, "DMA enable failed\n");
+@@ -1574,6 +1600,12 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
+ {
+ 	int nvec;
+ 
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+		return apcie_assign_irqs(pdev, n_ports);
+	}
+	#endif
+
+ 	if (hpriv->flags & AHCI_HFLAG_NO_MSI)
+ 		return -ENODEV;
+ 
+@@ -1700,6 +1732,13 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 
+ 	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+ 
+	
+	#ifdef CONFIG_X86_PS4
+	/* This will return negative on non-PS4 platforms */
+	if (apcie_status() == 0)
+		return -EPROBE_DEFER;
+	#endif
+
+ 	ata_print_version_once(&pdev->dev, DRV_VERSION);
+ 
+ 	/* The AHCI driver can only drive the SATA ports, the PATA driver
+@@ -1947,8 +1986,258 @@ static void ahci_remove_one(struct pci_dev *pdev)
+ 				     NULL);
+ 	pm_runtime_get_noresume(&pdev->dev);
+ 	ata_pci_remove_one(pdev);
+
+	#ifdef CONFIG_X86_PS4
+	if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+		apcie_free_irqs(pdev->irq, 1);
+	}
+	#endif
+}
+
+#ifdef CONFIG_X86_PS4
+void bpcie_sata_phy_init(struct device *dev, struct ahci_controller *ctlr)
+{
+	int i;
+	u32 v;
+	u32 v2;
+	bool is_phy_gen_3;
+	unsigned int trace_length;
+
+  	dev_info(dev, "Belize SATA PHY init\n");
+
+	for (i = 0; i < 100; i++) {
+		udelay(10000);
+	}
+
+ 	//step 1
+  	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x81);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff00) | 1);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xa5);
+
+	//step 2
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+
+	if (ctlr->dev_id == 0x90ca104d || ctlr->dev_id == 0x909f104d || ctlr->dev_id == 0x90d9104d) {
+		is_phy_gen_3 = false;
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xfffff3ff);
+	} else {
+		u32 v2 = bpcie_ahci_read(ctlr->r_mem, 0);
+	  	if ((v2 & 0xf00000) != 0x300000) {
+	    		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x400);
+	    		is_phy_gen_3 = false;
+	  	} else {
+	    		 dev_info(dev,"PHY SET GEN3\n");
+	    		 bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x800);
+	    		 is_phy_gen_3 = true;
+	  	}
+	}
+
+	//--- step 3 ---
+	if (ctlr->trace_len == 0) {
+	  	trace_length = 6;
+	} else {
+	  	trace_length = ctlr->trace_len & 0x1f;
+	  	if (trace_length >= 0x13) {
+	    		trace_length = 6;
+	  	}
+	}
+
+	dev_info(dev,"Belize SATA PHY Trace length : %d\n",trace_length);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xa3);
+
+	//--- step 4 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x800);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xd0);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff800) | 0x441);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xe1);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff8f) | 0x60);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xd0);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffff3fff) | 0x8000);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xf1);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x400);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x48);
+
+	//--- step 5 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, 0x62d8);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xe);
+
+	//--- step 6 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xffffdfff);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 1);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 1);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x91);
+
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 1);
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
+
+	//--- step 7 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	if (trace_length >= 0xe) {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x28);
+	} else {
+		if (trace_length < 0xb) {
+	    		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 8);
+	  	} else {
+	    		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x10);
+	  	}
+	}
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x12);
+
+	//--- step 8 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x91);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	if (trace_length < 5) {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x24);
+	} else {
+	  	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x2a);
+	}
+
+	//--- step 9 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xff);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, 1);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x97);
+
+	//--- step 10 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	if (is_phy_gen_3) {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff80) | 0xd3);
+	} else {
+	  	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff80) | 0xee);
+	}
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x95);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff00) | 0xee);
+
+	//--- step 11 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xff);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, 0);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
+
+	//--- step 12 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	if (trace_length < 0xe) {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0x900);
+	} else {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0xe00);
+	}
+
+	//--- step 13 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff07f) | 0x900);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x91);
+
+	//--- step 14 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	if (is_phy_gen_3) {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0xd00);
+	} else {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0xe80);
+	}
+
+	//--- step 15 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 200);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xffffefff);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 10);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xffffefff);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x82);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 0x1000);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xc9);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 0x1000);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x84);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc0) | 0xc);
+
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
+
+	//--- step 16 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	v = v & 0xffff0fff;
+	if (trace_length < 0xe) {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 0x8000);
+	} else {
+		bpcie_ahci_write(ctlr->r_mem, 0x17c, v);
+	}
+
+	//--- step 17 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+	bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffff0fff) | 0x8000);
+
+	//--- step 18 ---
+	bpcie_ahci_write(ctlr->r_mem, 0xa0, 0);
+	v = bpcie_ahci_read(ctlr->r_mem, 0xa4);
+	bpcie_ahci_write(ctlr->r_mem, 0xa4, v | 0x40);
+
+	//--- step 19 ---
+	if (ctlr->dev_id != 0x909f104d && ctlr->dev_id != 0x90ca104d && ctlr->dev_id != 0x90d9104d) {
+		v2 = 0x73000000;
+	} else {
+		v2 = 0x30000000;
+	}
+
+	//--- step 20 ---
+	bpcie_ahci_write(ctlr->r_mem, 0xa0, 4);
+	v = bpcie_ahci_read(ctlr->r_mem, 0xa4);
+	bpcie_ahci_write(ctlr->r_mem, 0xa4, (v & 0x88ffffff) | v2);
+
+	//--- step 21 ---
+	v = bpcie_ahci_read(ctlr->r_mem, 0xa4);
+
+	//--- step 22 ---
+	for (i = 0; i < 100; i++) {
+		udelay(10000);
+	}
+
+	//--- step 23 ---
+	bpcie_ahci_write(ctlr->r_mem, 0x178, 0xf9);
+	v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
+
+	if (is_phy_gen_3) {
+		dev_info(dev,"Align 90=0x%02x\n",v & 0x7f);
+	}
+	//done!
+ }
+ 
+EXPORT_SYMBOL_GPL(bpcie_sata_phy_init);
+#endif
+
+ module_pci_driver(ahci_pci_driver);
+ 
+ MODULE_AUTHOR("Jeff Garzik");
+diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
+index 60ae707a88cc..efdfac788727 100644
+--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
+@@ -447,4 +447,32 @@ static inline int ahci_nr_ports(u32 cap)
+ 	return (cap & 0x1f) + 1;
+ }
+ 
+#ifdef CONFIG_X86_PS4
+struct f_resource{
+	u64 resource_i_ptr;
+	u64 r_bustag;
+	void __iomem * r_bushandle;
+};
+
+struct ahci_controller{
+	void *dev;
+	int dev_id;
+	struct f_resource *r_mem;
+	u32 trace_len;
+};
+
+void bpcie_sata_phy_init(struct device *dev, struct ahci_controller *ctlr);
+
+static inline void bpcie_ahci_write(struct f_resource *r_mem, u32 offset, u32 val) {
+	iowrite32(val, r_mem->r_bushandle + offset);
+}
+
+static inline u32 bpcie_ahci_read(struct f_resource *r_mem, u32 offset) {
+		return ioread32(r_mem->r_bushandle + offset);
+}
+#endif
+
+
+
+
+ #endif /* _AHCI_H */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 752b66d7d0df..5e249922a72a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -1068,6 +1068,10 @@ static int gmc_v7_0_sw_init(void *handle)
+ 	if (r)
+ 		return r;
+ 
+
+	dev_info(adev->dev, "Done gart\n");
+
+
+ 	/*
+ 	 * number of VMs
+ 	 * VMID 0 is reserved for System
+@@ -1093,6 +1097,8 @@ static int gmc_v7_0_sw_init(void *handle)
+ 		return -ENOMEM;
+ 	atomic_set(&adev->gmc.vm_fault_info_updated, 0);
+ 
+	dev_info(adev->dev, "Done init\n");
+
+ 	return 0;
+ }
+ 
+diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
+index f20dc0c7b78f..4d36261e88a9 100644
+--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
+@@ -3300,6 +3300,7 @@ static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ 	if (devid < 0)
+ 		return 0;
+ 
+	pr_err("Remapping Selected: %x\n", devid);
+ 	iommu = amd_iommu_rlookup_table[devid];
+ 	return iommu && iommu->ir_domain == d;
+ }
+diff --git a/drivers/ps4/aeolia.h b/drivers/ps4/aeolia.h
+index 13df4b9a4fef..5319822ca818 100644
+--- a/drivers/ps4/aeolia.h
+++ b/drivers/ps4/aeolia.h
+@@ -151,11 +151,11 @@ struct apcie_dev {
+ 	struct apcie_icc_dev icc;
+ };
+ 
+-#define sc_err(...) dev_err(&sc->pdev->dev, __VA_ARGS__)
+-#define sc_warn(...) dev_warn(&sc->pdev->dev, __VA_ARGS__)
+-#define sc_notice(...) dev_notice(&sc->pdev->dev, __VA_ARGS__)
+#define sc_err(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+#define sc_warn(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+#define sc_notice(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+ #define sc_info(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+-#define sc_dbg(...) dev_dbg(&sc->pdev->dev, __VA_ARGS__)
+#define sc_dbg(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+ 
+ static inline int apcie_irqnum(struct apcie_dev *sc, int index)
+ {
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index d9c36f7715bb..f4e3a380d591 100644
+--- a/drivers/ps4/ps4-apcie.c
+++ b/drivers/ps4/ps4-apcie.c
+@@ -18,6 +18,11 @@
+ 
+ #include "aeolia.h"
+ 
+
+#define     MSI_DATA_VECTOR_SHIFT	0
+#define	    MSI_DATA_VECTOR(v)		(((u8)v) << MSI_DATA_VECTOR_SHIFT)
+#define     MSI_DATA_VECTOR_MASK	0xffffff00
+
+ /* #define QEMU_HACK_NO_IOMMU */
+ 
+ /* Number of implemented MSI registers per function */
+@@ -63,12 +68,20 @@ static void apcie_config_msi(struct apcie_dev *sc, u32 func, u32 subfunc,
+ 
+ 	glue_clear_mask(sc, APCIE_REG_MSI_CONTROL, APCIE_REG_MSI_CONTROL_ENABLE);
+ 	/* Unknown */
+	sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI(0x8), 0xffffffff);
+ 	glue_write32(sc, APCIE_REG_MSI(0x8), 0xffffffff);
+ 	/* Unknown */
+	sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI(0xc + (func << 2)), 0xB7FFFF00 + func * 16);
+ 	glue_write32(sc, APCIE_REG_MSI(0xc + (func << 2)), 0xB7FFFF00 + func * 16);
+
+	sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI_ADDR(func), addr);
+ 	glue_write32(sc, APCIE_REG_MSI_ADDR(func), addr);
+ 	/* Unknown */
+
+	sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI(0xcc + (func << 2)), 0);
+ 	glue_write32(sc, APCIE_REG_MSI(0xcc + (func << 2)), 0);
+
+	sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI_DATA_HI(func),  data & 0xffe0);
+ 	glue_write32(sc, APCIE_REG_MSI_DATA_HI(func), data & 0xffe0);
+ 
+ 	if (func < 4) {
+@@ -84,6 +97,8 @@ static void apcie_config_msi(struct apcie_dev *sc, u32 func, u32 subfunc,
+ 	} else {
+ 		offset = 0xa0 + ((func - 5) << 4) + (subfunc << 2);
+ 	}
+
+	sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4,  APCIE_REG_MSI_DATA_LO(offset), data & 0x1f);
+ 	glue_write32(sc, APCIE_REG_MSI_DATA_LO(offset), data & 0x1f);
+ 
+ 	if (func == AEOLIA_FUNC_ID_PCIE)
+@@ -149,9 +164,17 @@ static void apcie_msi_calc_mask(struct irq_data *data) {
+ static void apcie_irq_msi_compose_msg(struct irq_data *data,
+ 				       struct msi_msg *msg)
+ {
+-       __irq_msi_compose_msg(irqd_cfg(data), msg, false);
+-}
+	struct irq_cfg *cfg = irqd_cfg(data);
+ 
+	memset(msg, 0, sizeof(*msg));
+	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
+	msg->address_lo = 0xfee00000;// Just do it like this for now
+
+	// I know this is absolute horseshit, but it matches a known working kernel
+	msg->data = data->irq - 1;
+
+	pr_err("apcie_irq_msi_compose_msg\n");
+}
+ 
+ static struct irq_chip apcie_msi_controller = {
+ 	.name = "Aeolia-MSI",
+@@ -162,7 +185,7 @@ static struct irq_chip apcie_msi_controller = {
+ 	.irq_retrigger = irq_chip_retrigger_hierarchy,
+ 	.irq_compose_msi_msg = apcie_irq_msi_compose_msg,
+ 	.irq_write_msi_msg = apcie_msi_write_msg,
+-	.flags = IRQCHIP_SKIP_SET_WAKE,
+	.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP,
+ };
+ 
+ static irq_hw_number_t apcie_msi_get_hwirq(struct msi_domain_info *info,
+@@ -176,7 +199,7 @@ static int apcie_msi_init(struct irq_domain *domain,
+ 			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
+ {
+ 	struct irq_data *data;
+-	pr_devel("apcie_msi_init(%p, %p, %d, 0x%lx, %p)\n", domain, info, virq, hwirq, arg);
+	pr_err("apcie_msi_init(%p, %p, %d, 0x%lx, %p)\n", domain, info, virq, hwirq, arg);
+ 
+ 	data = irq_domain_get_irq_data(domain, virq);
+ 	irq_domain_set_info(domain, virq, hwirq, info->chip, info->chip_data,
+@@ -188,23 +211,25 @@ static int apcie_msi_init(struct irq_domain *domain,
+ static void apcie_msi_free(struct irq_domain *domain,
+ 			  struct msi_domain_info *info, unsigned int virq)
+ {
+-	pr_devel("apcie_msi_free(%d)\n", virq);
+	pr_err("apcie_msi_free(%d)\n", virq);
+ }
+ 
+-int apcie_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
+-		     msi_alloc_info_t *arg)
+
+static void apcie_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
+ {
+-	init_irq_alloc_info(arg, NULL);
+	arg->desc = desc;
+	struct pci_dev* device = msi_desc_to_pci_dev(desc);
+ 
+-	arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
+-	arg->flags |= MSI_FLAG_MULTI_PCI_MSI;
+	arg->hwirq = PCI_FUNC(device->devfn) << 8;
+ 
+-	return 0;
+#ifndef QEMU_HACK_NO_IOMMU
+	arg->hwirq |= 0xFF;
+#endif
+ }
+ 
+ static struct msi_domain_ops apcie_msi_domain_ops = {
+ 	.get_hwirq	= apcie_msi_get_hwirq,
+-	.msi_prepare	= apcie_msi_prepare,
+	.set_desc       = apcie_set_desc,
+ 	.msi_init	= apcie_msi_init,
+ 	.msi_free	= apcie_msi_free,
+ };
+@@ -219,7 +244,6 @@ static struct msi_domain_info apcie_msi_domain_info = {
+ 
+ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ {
+-	struct msi_domain_info *domain_info;
+ 	struct irq_domain *domain, *parent;
+ 	struct fwnode_handle *fn;
+ 	struct irq_fwspec fwspec;
+@@ -228,19 +252,15 @@ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ 	if (x86_vector_domain == NULL)
+ 		return NULL;
+ 
+-	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
+-	if (!domain_info)
+-		return NULL;
+-
+-	*domain_info = apcie_msi_domain_info;
+-	domain_info->chip_data = (void *)sc;
+	apcie_msi_domain_info.chip_data = (void *)sc;
+ 
+ 	fn = irq_domain_alloc_named_id_fwnode(apcie_msi_controller.name, pci_dev_id(sc->pdev));
+ 	if (!fn) {
+-		kfree(domain_info);
+ 		return NULL;
+ 	}
+ 
+	sc_dbg("devid = %d\n", pci_dev_id(sc->pdev));
+
+ 	fwspec.fwnode = fn;
+ 	fwspec.param_count = 1;
+ 
+@@ -249,17 +269,19 @@ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ 
+ 	parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
+ 	if (!parent) {
+		sc_dbg("no parent \n");
+ 		parent = x86_vector_domain;
+	} else if (parent == x86_vector_domain) {
+		sc_dbg("no parent \n");
+ 	} else {
+ 		apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
+ 		apcie_msi_controller.name = "IR-Aeolia-MSI";
+ 	}
+ 
+-	domain = msi_create_irq_domain(fn, domain_info, parent);
+	domain = msi_create_irq_domain(fn, &apcie_msi_domain_info, parent);
+ 	if (!domain) {
+ 		irq_domain_free_fwnode(fn);
+-		kfree(domain_info);
+-		pr_warn("Failed to initialize IR-Aeolia-MSI irqdomain.\n");
+		pr_warn("Failed to initialize Aeolia-MSI irqdomain.\n");
+ 	}
+ 
+ 	return domain;
+@@ -302,15 +324,17 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ 	info.type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
+ 	/* IRQs "come from" function 4 as far as the IOMMU/system see */
+ 	//info.msi_dev = sc->pdev;
+-	info.desc = alloc_msi_entry(&dev->dev, nvec, NULL);
+	info.devid = pci_dev_id(sc->pdev);
+
+	int i, base = 0;
+	struct msi_desc *desc;
+	struct device* bare_dev = &sc->pdev->dev;
+
+ 	/* Our hwirq number is function << 8 plus subfunction.
+ 	 * Subfunction is usually 0 and implicitly increments per hwirq,
+ 	 * but can also be 0xff to indicate that this is a shared IRQ. */
+-	//https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=3b9c1d377d67072d1d8a2373b4969103cca00dab
+ 	info.hwirq = PCI_FUNC(dev->devfn) << 8;
+ 
+-	dev_dbg(&dev->dev, "apcie_assign_irqs(%d)\n", nvec);
+-
+ #ifndef QEMU_HACK_NO_IOMMU
+ 	info.flags = X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
+ 	if (!(apcie_msi_domain_info.flags & MSI_FLAG_MULTI_PCI_MSI)) {
+@@ -319,14 +343,23 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ 	}
+ #endif
+ 
+	desc = alloc_msi_entry(bare_dev, 1, NULL);
+
+	info.desc = desc;
+	info.data = sc;
+
+	dev_info(&dev->dev, "apcie_assign_irqs(%d) (%d)\n", nvec, info.hwirq);
+
+ 	ret = irq_domain_alloc_irqs(sc->irqdomain, nvec, NUMA_NO_NODE, &info);
+ 	if (ret >= 0) {
+		dev_info(&dev->dev, "irq_domain_alloc_irqs = %x\n", ret);
+ 		dev->irq = ret;
+		desc->irq = ret;
+ 		ret = nvec;
+ 	}
+ 
+ fail:
+-	dev_dbg(&dev->dev, "apcie_assign_irqs returning %d\n", ret);
+	dev_info(&dev->dev, "apcie_assign_irqs returning %d\n", ret);
+ 	if (sc_dev)
+ 		pci_dev_put(sc_dev);
+ 	return ret;
+@@ -494,10 +527,10 @@ static int apcie_probe(struct pci_dev *dev, const struct pci_device_id *id) {
+ 
+ 	if ((ret = apcie_glue_init(sc)) < 0)
+ 		goto free_bars;
+-	if ((ret = apcie_uart_init(sc)) < 0)
+-		goto remove_glue;
+	//if ((ret = apcie_uart_init(sc)) < 0)
+	//	goto remove_glue;
+ 	if ((ret = apcie_icc_init(sc)) < 0)
+-		goto remove_uart;
+		goto remove_glue;
+ 
+ 	apcie_initialized = true;
+ 	return 0;
+-- 
+2.45.1
+
@@ -0,0 +1,126 @@
+From ed61a42f4a35bf12c7a78642f7d814f50b936f57 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Sat, 25 Dec 2021 16:13:58 +0100
+Subject: [PATCH 11/22] fix: incorrectly applied patches and missing patches
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c              |  3 +++
+ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c  |  2 ++
+ drivers/gpu/drm/radeon/cik.c                       | 14 +++++++-------
+ drivers/ps4/ps4-apcie.c                            |  1 +
+ 4 files changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index d81187445ebe..8513dd006ad5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -1400,11 +1400,14 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
+ 	    (adev->asic_type == CHIP_GLADIUS)) {
+ 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+ 		err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+		if (err)
+ 		{
+ 			pr_err("gfx7: Failed to open firmware \"%s\"\n", fw_name);
+ 			goto out;
+ 		}
+
+ 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
+		if (err)
+ 		{
+ 			pr_err("gfx7: Failed to validate ucode firmware \"%s\"\n", fw_name);
+ 			goto out;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index d88513d0aca0..0ddcd498a68b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1860,6 +1860,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+ 
+ 	switch (dev->device_info->asic_family) {
+ 	/* HWS is not available on Hawaii. */
+	case CHIP_LIVERPOOL:
+	case CHIP_GLADIUS:
+ 	case CHIP_HAWAII:
+ 	/* HWS depends on CWSR for timely dequeue. CWSR is not
+ 	 * available on Tonga.
+diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
+index f6ca400c006f..a0b83b91fdac 100644
+--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
+@@ -8251,7 +8251,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 		return IRQ_NONE;
+ 
+ 	rptr = rdev->ih.rptr;
+-	DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
+	//DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
+ 
+ 	/* Order reading of wptr vs. reading of IH ring data */
+ 	rmb();
+@@ -8294,7 +8294,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 
+ 				break;
+ 			default:
+-				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+				//DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ 				break;
+ 			}
+ 			break;
+@@ -8324,7 +8324,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 
+ 				break;
+ 			default:
+-				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+				//DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ 				break;
+ 			}
+ 			break;
+@@ -8354,7 +8354,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 
+ 				break;
+ 			default:
+-				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+				//DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ 				break;
+ 			}
+ 			break;
+@@ -8384,7 +8384,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 
+ 				break;
+ 			default:
+-				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+				//DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ 				break;
+ 			}
+ 			break;
+@@ -8414,7 +8414,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 
+ 				break;
+ 			default:
+-				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+				//DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ 				break;
+ 			}
+ 			break;
+@@ -8444,7 +8444,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ 
+ 				break;
+ 			default:
+-				DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+				//DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ 				break;
+ 			}
+ 			break;
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index f4e3a380d591..fd27a4f38e61 100644
+--- a/drivers/ps4/ps4-apcie.c
+++ b/drivers/ps4/ps4-apcie.c
+@@ -527,6 +527,7 @@ static int apcie_probe(struct pci_dev *dev, const struct pci_device_id *id) {
+ 
+ 	if ((ret = apcie_glue_init(sc)) < 0)
+ 		goto free_bars;
+	// TODO (ps4patches): figure out why this dies a horrible and painful death.
+ 	//if ((ret = apcie_uart_init(sc)) < 0)
+ 	//	goto remove_glue;
+ 	if ((ret = apcie_icc_init(sc)) < 0)
+-- 
+2.45.1
+
@@ -0,0 +1,188 @@
+From b009aedae1dd07fa3c761e7ddcc92071dd792853 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Tue, 28 Dec 2021 17:53:53 +0100
+Subject: [PATCH 12/22] fix: radeon drivers
+
+---
+ drivers/gpu/drm/radeon/cik.c          | 30 +++++++++++++--------------
+ drivers/gpu/drm/radeon/ps4_bridge.c   | 23 +++++++++++---------
+ drivers/gpu/drm/radeon/radeon.h       |  2 +-
+ drivers/gpu/drm/radeon/radeon_audio.c |  2 +-
+ 4 files changed, 30 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
+index a0b83b91fdac..ce9799517ff4 100644
+--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
+@@ -1038,7 +1038,20 @@ static const u32 kalindi_rlc_save_restore_register_list[] =
+ 	(0x0e00 << 16) | (0x9600 >> 2),
+ };
+ 
+-static const u32 liverpool_rlc_save_restore_register_li
+static const u32 bonaire_golden_spm_registers[] =
+{
+	0x30800, 0xe0ffffff, 0xe0000000
+};
+
+static const u32 bonaire_golden_common_registers[] =
+{
+	0xc770, 0xffffffff, 0x00000800,
+	0xc774, 0xffffffff, 0x00000800,
+	0xc798, 0xffffffff, 0x00007fbf,
+	0xc79c, 0xffffffff, 0x00007faf
+};
+
+static const u32 liverpool_rlc_save_restore_register_list[] =
+ {
+ 	(0x0600 << 16) | 0x263d,
+ 	0x00000000,
+@@ -1453,19 +1466,6 @@ static const u32 liverpool_rlc_save_restore_register_li
+ 	(0x0e00 << 16) | 0x230d,
+ };
+ 
+-static const u32 bonaire_golden_spm_registers[] =
+-{
+-	0x30800, 0xe0ffffff, 0xe0000000
+-};
+-
+-static const u32 bonaire_golden_common_registers[] =
+-{
+-	0xc770, 0xffffffff, 0x00000800,
+-	0xc774, 0xffffffff, 0x00000800,
+-	0xc798, 0xffffffff, 0x00007fbf,
+-	0xc79c, 0xffffffff, 0x00007faf
+-};
+-
+ static const u32 bonaire_golden_registers[] =
+ {
+ 	0x3354, 0x00000333, 0x00000333,
+@@ -1616,7 +1616,7 @@ static const u32 liverpool_golden_common_registers[] =
+ 	0x5004, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
+ };
+ 
+-onst u32 liverpool_golden_registers[] =
+static const u32 liverpool_golden_registers[] =
+ {
+ 	0xc420, 0xffffffff, 0xfffffffc, /* RLC_CGTT_MGCG_OVERRIDE */
+ 	0x30800, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
+diff --git a/drivers/gpu/drm/radeon/ps4_bridge.c b/drivers/gpu/drm/radeon/ps4_bridge.c
+index 1c1cb0b4dabb..6f6e354e182d 100644
+--- a/drivers/gpu/drm/radeon/ps4_bridge.c
+++ b/drivers/gpu/drm/radeon/ps4_bridge.c
+@@ -13,11 +13,14 @@
+ 
+ #include <asm/ps4.h>
+ 
+#include <drm/drm_bridge.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_edid.h>
+-#include <drm/drmP.h>
+#include <drm/drm_print.h>
+
+#include <linux/pci.h>
+ 
+ #include "radeon_mode.h"
+ #include "ObjectID.h"
+@@ -95,7 +98,6 @@
+ # define HDCPEN_ENC_EN 0x03
+ # define HDCPEN_ENC_DIS 0x05
+ 
+-#define PCI_VENDOR_ID_AMD 0x1002
+ #define PCI_DEVICE_ID_CUH_11XX 0x9920
+ #define PCI_DEVICE_ID_CUH_12XX 0x9922
+ #define PCI_DEVICE_ID_CUH_2XXX 0x9923
+@@ -269,8 +271,8 @@ static inline struct radeon_ps4_bridge *
+ }
+ 
+ static void radeon_ps4_bridge_mode_set(struct drm_bridge *bridge,
+-			      struct drm_display_mode *mode,
+-			      struct drm_display_mode *adjusted_mode)
+			      const struct drm_display_mode *mode,
+			      const struct drm_display_mode *adjusted_mode)
+ {
+ 	struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
+ 
+@@ -357,7 +359,7 @@ static void radeon_ps4_bridge_enable(struct drm_bridge *bridge)
+ 	struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
+ 	struct drm_connector *connector = mn_bridge->connector;
+ 	struct drm_device *dev = connector->dev;
+-	struct pci_dev *pdev = dev->pdev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
+ 	u8 dp[3];
+ 
+ 	if (!mn_bridge->mode) {
+@@ -638,21 +640,21 @@ static const struct drm_display_mode mode_480p = {
+ 	DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
+ 		 752, 800, 0, 480, 490, 492, 525, 0,
+ 		 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+-	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3
+	.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3
+ };
+ /* 4 - 1280x720@60Hz */
+ static const struct drm_display_mode mode_720p = {
+ 	DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
+ 		 1430, 1650, 0, 720, 725, 730, 750, 0,
+ 		 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+-	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
+	.picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
+ };
+ /* 16 - 1920x1080@60Hz */
+ static const struct drm_display_mode mode_1080p = {
+ 	DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
+ 		 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
+ 		 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+-	.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
+	.picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
+ };
+ 
+ int radeon_ps4_bridge_get_modes(struct drm_connector *connector)
+@@ -669,7 +671,7 @@ int radeon_ps4_bridge_get_modes(struct drm_connector *connector)
+ 	//newmode = drm_mode_duplicate(dev, &mode_480p);
+ 	//drm_mode_probed_add(connector, newmode);
+ 
+-	drm_mode_connector_update_edid_property(connector, NULL);
+	drm_connector_update_edid_property(connector, NULL);
+ 
+ 	return 0;
+ }
+@@ -718,7 +720,8 @@ int radeon_ps4_bridge_mode_valid(struct drm_connector *connector,
+ 	return MODE_OK;
+ }
+ 
+-static int radeon_ps4_bridge_attach(struct drm_bridge *bridge)
+static int radeon_ps4_bridge_attach(struct drm_bridge *bridge,
+				    enum drm_bridge_attach_flags flags)
+ {
+ 	/* struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge); */
+ 
+diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
+index 314fd436f3c9..05cbdf9e6dfe 100644
+--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
+@@ -2679,7 +2679,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
+ #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
+ #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
+ #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
+-			     (rdev->family == CHIP_MULLINS || \
+			     (rdev->family == CHIP_MULLINS) ||            \
+ 			     (rdev->family == CHIP_LIVERPOOL))
+ 
+ #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
+diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c
+index ba877d0b73fd..3bca01e82835 100644
+--- a/drivers/gpu/drm/radeon/radeon_audio.c
+++ b/drivers/gpu/drm/radeon/radeon_audio.c
+@@ -244,7 +244,7 @@ int radeon_audio_init(struct radeon_device *rdev)
+ 
+ 	rdev->audio.enabled = true;
+ 
+-	if (ASIC_IS_DCE83(rdev))		/* KB: 2 streams, 3 endpoints */
+	if (ASIC_IS_DCE83(rdev))	/* KB: 2 streams, 3 endpoints */
+ 		rdev->audio.num_pins = 3;
+ 	else if (ASIC_IS_DCE81(rdev))	/* KV: 4 streams, 7 endpoints */
+ 		rdev->audio.num_pins = 7;
+-- 
+2.45.1
+
@@ -0,0 +1,53 @@
+From 1b9c84e8afd63df84109a717f6fe3076f2990841 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Tue, 28 Dec 2021 18:49:46 +0100
+Subject: [PATCH 13/22] fix: amdgpu drivers
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c   | 2 +-
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c       | 2 +-
+ drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+index 619d4c771176..dc517dc8ae94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+@@ -41,7 +41,7 @@ static void amdgpu_maybe_add_bridge(struct drm_connector *connector,
+ 				    struct drm_encoder *encoder)
+ {
+ 	struct drm_device *dev = connector->dev;
+-	struct amdgpu_device *adev = dev->dev_private;
+	struct amdgpu_device *adev = drm_to_adev(dev);
+ 
+ 	if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
+ 		ps4_bridge_register(connector, encoder);
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index 33987ecdc517..a41352dbe298 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -262,7 +262,7 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
+ 	unsigned lane_num, i, max_pix_clock;
+ 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ 	struct drm_device *dev = amdgpu_connector->base.dev;
+-	struct amdgpu_device *adev = dev->dev_private;
+	struct amdgpu_device *adev = drm_to_adev(dev);
+ 
+ 	/* Liverpool is always connected to an encoder that needs 4 lanes */
+ 	if (adev->asic_type == CHIP_LIVERPOOL)
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+index 5bd8a782feb5..801178479719 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+@@ -446,7 +446,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
+ 	struct amdgpu_connector_atom_dig *dig_connector;
+ 
+ 	struct drm_device *dev = encoder->dev;
+-	struct amdgpu_device *adev = dev->dev_private;
+	struct amdgpu_device *adev = drm_to_adev(dev);
+ 
+ 	/* dp bridges are always DP */
+ 	if ((amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) ||
+-- 
+2.45.1
+
@@ -0,0 +1,191 @@
+From 3b2f7c502e713f75cd73793657eb58b55121d8c6 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Wed, 29 Dec 2021 14:16:57 +0100
+Subject: [PATCH 14/22] fix: re-add legacy bridge functions
+
+---
+ config                                  |  2 +-
+ drivers/gpu/drm/amd/amdgpu/ps4_bridge.c | 20 +++++++------
+ drivers/gpu/drm/drm_crtc_helper.c       | 37 +++++++++++++++++++++++++
+ 3 files changed, 50 insertions(+), 9 deletions(-)
+
+diff --git a/config b/config
+index 9b3e8c78ecf1..ceaac7d2d935 100644
+--- a/config
+++ b/config
+@@ -2262,7 +2262,7 @@ CONFIG_DRM_SCHED=y
+ CONFIG_DRM_AMDGPU=y
+ # CONFIG_DRM_AMDGPU_SI is not set
+ CONFIG_DRM_AMDGPU_CIK=y
+-CONFIG_DRM_AMDGPU_USERPTR=y
+# CONFIG_DRM_AMDGPU_USERPTR is not set
+ 
+ #
+ # ACP (Audio CoProcessor) Configuration
+diff --git a/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c b/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+index 86af15c134c4..d63ae6dddbb2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+++ b/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+@@ -11,6 +11,10 @@
+  * GNU General Public License for more details.
+  */
+ 
+
+// TODO (ps4patches): Make functions atomic,
+//  https://lore.kernel.org/linux-arm-kernel/20211020181901.2114645-5-sam@ravnborg.org/
+
+ #include <asm/ps4.h>
+ 
+ #include <drm/drm_crtc.h>
+@@ -676,7 +680,7 @@ int ps4_bridge_get_modes(struct drm_connector *connector)
+ {
+ 	struct drm_device *dev = connector->dev;
+ 	struct drm_display_mode *newmode;
+-	DRM_DEBUG_KMS("ps4_bridge_get_modes\n");
+	pr_info("ps4_bridge_get_modes\n");
+ 
+ 	newmode = drm_mode_duplicate(dev, &mode_1080p);
+ 	drm_mode_probed_add(connector, newmode);
+@@ -687,7 +691,7 @@ int ps4_bridge_get_modes(struct drm_connector *connector)
+ 	//drm_mode_probed_add(connector, newmode);
+ 
+ 	drm_connector_update_edid_property(connector, NULL);
+-    
+
+ 	return 0;
+ }
+ 
+@@ -738,7 +742,6 @@ int ps4_bridge_mode_valid(struct drm_connector *connector,
+ static int ps4_bridge_attach(struct drm_bridge *bridge,
+ 			     enum drm_bridge_attach_flags flags)
+ {
+-	// TODO (ps4patches): Why is this in comments?
+ 	/* struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge); */
+ 
+ 	return 0;
+@@ -761,16 +764,17 @@ int ps4_bridge_register(struct drm_connector *connector,
+ 
+ 	mn_bridge->encoder = encoder;
+ 	mn_bridge->connector = connector;
+	mn_bridge->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+ 	mn_bridge->bridge.funcs = &ps4_bridge_funcs;
+-	ret = drm_bridge_attach(mn_bridge->encoder, &mn_bridge->bridge, NULL, 0);
+
+	// TODO (ps4patches): This seems to be the new way of adding bridges
+	drm_bridge_add(&mn_bridge->bridge);
+
+	ret = drm_bridge_attach(mn_bridge->encoder, &mn_bridge->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ 	if (ret) {
+ 		DRM_ERROR("Failed to initialize bridge with drm\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	//encoder->bridge = &mn_bridge->bridge;
+-	// TODO (ps4patches): This seems to be the new way of adding bridges
+-	drm_bridge_add(&mn_bridge->bridge);
+-
+ 	return 0;
+ }
+diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
+index bff917531f33..17bf9a7ff546 100644
+--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
+@@ -162,10 +162,15 @@ drm_encoder_disable(struct drm_encoder *encoder)
+ 	if (!encoder_funcs)
+ 		return;
+ 
+	struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+	drm_bridge_chain_disable(bridge);
+
+ 	if (encoder_funcs->disable)
+ 		(*encoder_funcs->disable)(encoder);
+ 	else if (encoder_funcs->dpms)
+ 		(*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
+
+	drm_bridge_chain_post_disable(bridge);
+ }
+ 
+ static void __drm_helper_disable_unused_functions(struct drm_device *dev)
+@@ -322,6 +327,14 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ 		if (!encoder_funcs)
+ 			continue;
+ 
+		struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+		ret = drm_bridge_chain_mode_fixup(bridge,
+					    mode, adjusted_mode);
+		if (!ret) {
+			DRM_DEBUG_KMS("Bridge fixup failed\n");
+			goto done;
+		}
+
+ 		encoder_funcs = encoder->helper_private;
+ 		if (encoder_funcs->mode_fixup) {
+ 			if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
+@@ -353,9 +366,14 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ 		if (!encoder_funcs)
+ 			continue;
+ 
+		struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+		drm_bridge_chain_disable(bridge);
+
+ 		/* Disable the encoders as the first thing we do. */
+ 		if (encoder_funcs->prepare)
+ 			encoder_funcs->prepare(encoder);
+
+		drm_bridge_chain_post_disable(bridge);
+ 	}
+ 
+ 	drm_crtc_prepare_encoders(dev);
+@@ -382,6 +400,9 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ 			encoder->base.id, encoder->name, mode->name);
+ 		if (encoder_funcs->mode_set)
+ 			encoder_funcs->mode_set(encoder, mode, adjusted_mode);
+
+		struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+		drm_bridge_chain_mode_set(bridge, mode, adjusted_mode);
+ 	}
+ 
+ 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
+@@ -396,8 +417,13 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ 		if (!encoder_funcs)
+ 			continue;
+ 
+		struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+		drm_bridge_chain_pre_enable(bridge);
+
+ 		if (encoder_funcs->commit)
+ 			encoder_funcs->commit(encoder);
+
+		drm_bridge_chain_enable(bridge);
+ 	}
+ 
+ 	/* Calculate and store various constants which
+@@ -816,14 +842,25 @@ static int drm_helper_choose_encoder_dpms(struct drm_encoder *encoder)
+ /* Helper which handles bridge ordering around encoder dpms */
+ static void drm_helper_encoder_dpms(struct drm_encoder *encoder, int mode)
+ {
+	struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+ 	const struct drm_encoder_helper_funcs *encoder_funcs;
+ 
+ 	encoder_funcs = encoder->helper_private;
+ 	if (!encoder_funcs)
+ 		return;
+ 
+	if (mode == DRM_MODE_DPMS_ON)
+		drm_bridge_chain_pre_enable(bridge);
+	else
+		drm_bridge_chain_disable(bridge);
+
+ 	if (encoder_funcs->dpms)
+ 		encoder_funcs->dpms(encoder, mode);
+
+	if (mode == DRM_MODE_DPMS_ON)
+		drm_bridge_chain_enable(bridge);
+	else
+		drm_bridge_chain_post_disable(bridge);
+ }
+ 
+ static int drm_helper_choose_crtc_dpms(struct drm_crtc *crtc)
+-- 
+2.45.1
+
@@ -0,0 +1,644 @@
+From 00879e27dddefbe1c062f53b4eec0e9166780a2a Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Wed, 29 Dec 2021 15:43:55 +0100
+Subject: [PATCH 15/22] feat: potentially added belize ahci support in a
+ universal way
+
+---
+ drivers/usb/host/xhci-aeolia.c | 543 ++++++++++++++++-----------------
+ 1 file changed, 268 insertions(+), 275 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-aeolia.c b/drivers/usb/host/xhci-aeolia.c
+index a9b345284495..1401af61430c 100644
+--- a/drivers/usb/host/xhci-aeolia.c
+++ b/drivers/usb/host/xhci-aeolia.c
+@@ -25,8 +25,7 @@ static struct hc_driver __read_mostly xhci_aeolia_hc_driver;
+ #define NR_DEVICES 3
+ 
+ struct aeolia_xhci {
+-	// TODO (ps4patches): Belize, enable in ahci commit
+-	// struct ata_host *host;
+	struct ata_host *host;
+ 	int nr_irqs;
+ 	struct usb_hcd *hcd[NR_DEVICES];
+ };
+@@ -75,14 +74,8 @@ static int xhci_aeolia_probe_one(struct pci_dev *dev, int index)
+ 	hcd->rsrc_start = pci_resource_start(dev, 2 * index);
+ 	hcd->rsrc_len = pci_resource_len(dev, 2 * index);
+ 
+-	/*
+-	 *  TODO (ps4patches): Belize, enable in ahci commit
+ 	if (!devm_request_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len,
+ 			driver->description)) {
+-	*/
+-
+-	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+-			     driver->description)) {
+ 		dev_dbg(&dev->dev, "controller already in use\n");
+ 		retval = -EBUSY;
+ 		goto put_hcd;
+@@ -124,9 +117,7 @@ static int xhci_aeolia_probe_one(struct pci_dev *dev, int index)
+ unmap_registers:
+ 	iounmap(hcd->regs);
+ release_mem_region:
+-	//
+-	// devm_release_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len);
+-	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	devm_release_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len);
+ put_hcd:
+ 	usb_put_hcd(hcd);
+ 	dev_err(&dev->dev, "init %s(%d) fail, %d\n",
+@@ -147,226 +138,225 @@ static void xhci_aeolia_remove_one(struct pci_dev *dev, int index)
+ 	usb_remove_hcd(xhci->shared_hcd);
+ 	usb_remove_hcd(hcd);
+ 	usb_put_hcd(xhci->shared_hcd);
+-	iounmap(hcd->regs);
+
+	// TODO (ps4patches): Does this really need to be disabled?
+	if(dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
+		iounmap(hcd->regs);
+	}
+ 	usb_put_hcd(hcd);
+ 	axhci->hcd[index] = NULL;
+ }
+ 
+-// TODO (ps4patches): Belize, enable in ahci commit
+-//#define DRV_VERSION	"3.0"
+-//#define DRV_NAME	"ahci"
+-//static const struct ata_port_info ahci_port_info = {
+-//	.flags		= AHCI_FLAG_COMMON,
+-//	.pio_mask	= ATA_PIO4,
+-//	.udma_mask	= ATA_UDMA6,
+-//	.port_ops	= &ahci_ops,
+-//};
+-//
+-//static struct scsi_host_template ahci_sht = {
+-//	AHCI_SHT(DRV_NAME),
+-//};
+-//
+-//static bool bus_master;
+-//static int ahci_init_one(struct pci_dev *pdev)
+-//{
+-//	struct f_resource* r_mem;
+-//	struct ahci_controller* ctlr;
+-//	struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+-//	struct ata_port_info pi = ahci_port_info;
+-//	const struct ata_port_info *ppi[] = { &pi, NULL };
+-//	struct ahci_host_priv *hpriv;
+-//      struct ata_host *host;
+-//	int n_ports, i, rc;
+-//	int ahci_pci_bar = 2;
+-//	resource_size_t		rsrc_start;
+-//	resource_size_t		rsrc_len;
+-//
+-//	VPRINTK("ENTER\n");
+-//
+-//	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+-//
+-//	ata_print_version_once(&pdev->dev, DRV_VERSION);
+-//
+-//	/*
+-//	rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
+-//	if (rc == -EBUSY)
+-//		pcim_pin_device(pdev);
+-//	if (rc)
+-//		return rc;
+-//	*/
+-//
+-//	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
+-//	//hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+-//	if (!hpriv)
+-//		return -ENOMEM;
+-//	hpriv->flags |= (unsigned long)pi.private_data;
+-//
+-//	//hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
+-//	rsrc_start = pci_resource_start(pdev, ahci_pci_bar);
+-//	rsrc_len = pci_resource_len(pdev, ahci_pci_bar);
+-//	//if (!request_mem_region(rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+-//	if (!devm_request_mem_region(&pdev->dev, rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+-//		dev_dbg(&pdev->dev, "controller already in use\n");
+-//		rc = -EBUSY;
+-//		goto put_hpriv;
+-//	}
+-//
+-//
+-//	hpriv->mmio = pci_ioremap_bar(pdev, ahci_pci_bar);
+-//	if (hpriv->mmio == NULL) {
+-//		dev_dbg(&pdev->dev, "error mapping memory\n");
+-//		rc = -EFAULT;
+-//		goto release_mem_region;
+-//	}
+-//
+-//	r_mem = kzalloc(sizeof(*r_mem), GFP_KERNEL);
+-//	if (r_mem) {
+-//		r_mem->r_bustag = 1;//mem
+-//		r_mem->r_bushandle = hpriv->mmio;
+-//
+-//		ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
+-//		if (ctlr) {
+-//			ctlr->r_mem = r_mem;
+-//			ctlr->dev_id = 0; //or 0x90ca104d;
+-//			ctlr->trace_len = 6;
+-//			bpcie_sata_phy_init(&pdev->dev, ctlr);
+-//			kfree(ctlr);
+-//		}
+-//		kfree(r_mem);
+-//	}
+-//	device_wakeup_enable(&pdev->dev);
+-//
+-//	/* save initial config */
+-//	ahci_save_initial_config(&pdev->dev, hpriv);
+-//
+-//	/* prepare host */
+-//	if (hpriv->cap & HOST_CAP_NCQ) {
+-//		pi.flags |= ATA_FLAG_NCQ;
+-//		/*
+-//		 * Auto-activate optimization is supposed to be
+-//		 * supported on all AHCI controllers indicating NCQ
+-//		 * capability, but it seems to be broken on some
+-//		 * chipsets including NVIDIAs.
+-//		 */
+-//		if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
+-//			pi.flags |= ATA_FLAG_FPDMA_AA;
+-//
+-//		/*
+-//		 * All AHCI controllers should be forward-compatible
+-//		 * with the new auxiliary field. This code should be
+-//		 * conditionalized if any buggy AHCI controllers are
+-//		 * encountered.
+-//		 */
+-//		pi.flags |= ATA_FLAG_FPDMA_AUX;
+-//	}
+-//
+-//	if (hpriv->cap & HOST_CAP_PMP)
+-//		pi.flags |= ATA_FLAG_PMP;
+-//
+-//	ahci_set_em_messages(hpriv, &pi);
+-//
+-//	/* CAP.NP sometimes indicate the index of the last enabled
+-//	 * port, at other times, that of the last possible port, so
+-//	 * determining the maximum port number requires looking at
+-//	 * both CAP.NP and port_map.
+-//	 */
+-//	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+-//
+-//	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
+-//	if (!host) {
+-//		rc = -ENOMEM;
+-//		goto unmap_registers;
+-//	}
+-//	axhci->host = host;
+-//	pci_set_drvdata(pdev, axhci);
+-//
+-//	host->private_data = hpriv;
+-//
+-//	{
+-//		int index = 1;
+-//		int irq = (axhci->nr_irqs > 1) ? (pdev->irq + index) : pdev->irq;
+-//		hpriv->irq = irq;
+-//	}
+-//
+-//	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+-//		host->flags |= ATA_HOST_PARALLEL_SCAN;
+-//	else
+-//		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
+-//
+-//	if (pi.flags & ATA_FLAG_EM)
+-//		ahci_reset_em(host);
+-//
+-//	for (i = 0; i < host->n_ports; i++) {
+-//		struct ata_port *ap = host->ports[i];
+-//
+-//		ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
+-//		ata_port_pbar_desc(ap, ahci_pci_bar,
+-//				   0x100 + ap->port_no * 0x80, "port");
+-//
+-//		/* set enclosure management message type */
+-//		if (ap->flags & ATA_FLAG_EM)
+-//			ap->em_message_type = hpriv->em_msg_type;
+-//
+-//
+-//		/* disabled/not-implemented port */
+-//		if (!(hpriv->port_map & (1 << i)))
+-//			ap->ops = &ata_dummy_port_ops;
+-//	}
+-//
+-//	rc = ahci_reset_controller(host);
+-//	dev_dbg(&pdev->dev, "ahci_reset_controller returned %d\n", rc);
+-//	if (rc)
+-//		goto release_host;
+-//
+-//	ahci_init_controller(host);
+-//	ahci_print_info(host, "ATA");
+-//
+-//	if (!bus_master) {
+-//		pci_set_master(pdev);
+-//		bus_master = true;
+-//	}
+-//
+-//	rc = ahci_host_activate(host, &ahci_sht);
+-//	dev_dbg(&pdev->dev, "ahci_host_activate returned %d\n", rc);
+-//	if (rc) {
+-//		goto host_deactivate;
+-//	}
+-//
+-//	pm_runtime_put_noidle(&pdev->dev);
+-//	return 0;
+-//
+-//	host_deactivate:
+-//	release_host:
+-//	unmap_registers:
+-//		iounmap(hpriv->mmio);
+-//	release_mem_region:
+-//
+-//		release_mem_region(rsrc_start, rsrc_len);
+-//
+-//		// TODO (ps4patches): Belize, enable in ahci commit
+-//		//devm_release_mem_region(&pdev->dev, rsrc_start, rsrc_len);
+-//	put_hpriv:
+-//		//kfree(hpriv);
+-//		devm_kfree(&pdev->dev, hpriv);
+-//		dev_err(&pdev->dev, "init %s fail, %d\n",
+-//				pci_name(pdev), rc);
+-//	return rc;
+-//}
+-//
+-//static void ahci_remove_one(struct pci_dev *pdev)
+-//{
+-//	pm_runtime_get_noresume(&pdev->dev);
+-//
+-//	struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+-//	if (axhci && axhci->host) {
+-//		ata_host_detach(axhci->host);
+-//		struct ahci_host_priv *hpriv = axhci->host->private_data;
+-//		if (hpriv) {
+-//			iounmap(hpriv->mmio);
+-//		}
+-//		axhci->host = NULL;
+-//	}
+-//}
+#define DRV_VERSION	"3.0"
+#define DRV_NAME	"ahci"
+static const struct ata_port_info ahci_port_info = {
+	.flags		= AHCI_FLAG_COMMON,
+	.pio_mask	= ATA_PIO4,
+	.udma_mask	= ATA_UDMA6,
+	.port_ops	= &ahci_ops,
+};
+
+static struct scsi_host_template ahci_sht = {
+	AHCI_SHT(DRV_NAME),
+};
+
+static bool bus_master;
+static int ahci_init_one(struct pci_dev *pdev)
+{
+	struct f_resource* r_mem;
+	struct ahci_controller* ctlr;
+	struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+	struct ata_port_info pi = ahci_port_info;
+	const struct ata_port_info *ppi[] = { &pi, NULL };
+	struct ahci_host_priv *hpriv;
+      struct ata_host *host;
+	int n_ports, i, rc;
+	int ahci_pci_bar = 2;
+	resource_size_t		rsrc_start;
+	resource_size_t		rsrc_len;
+
+	VPRINTK("ENTER\n");
+
+	WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+
+	ata_print_version_once(&pdev->dev, DRV_VERSION);
+
+	/*
+	rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
+	if (rc == -EBUSY)
+		pcim_pin_device(pdev);
+	if (rc)
+		return rc;
+	*/
+
+	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
+	//hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+	if (!hpriv)
+		return -ENOMEM;
+	hpriv->flags |= (unsigned long)pi.private_data;
+
+	//hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
+	rsrc_start = pci_resource_start(pdev, ahci_pci_bar);
+	rsrc_len = pci_resource_len(pdev, ahci_pci_bar);
+	//if (!request_mem_region(rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+	if (!devm_request_mem_region(&pdev->dev, rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+		dev_dbg(&pdev->dev, "controller already in use\n");
+		rc = -EBUSY;
+		goto put_hpriv;
+	}
+
+
+	hpriv->mmio = pci_ioremap_bar(pdev, ahci_pci_bar);
+	if (hpriv->mmio == NULL) {
+		dev_dbg(&pdev->dev, "error mapping memory\n");
+		rc = -EFAULT;
+		goto release_mem_region;
+	}
+
+	r_mem = kzalloc(sizeof(*r_mem), GFP_KERNEL);
+	if (r_mem) {
+		r_mem->r_bustag = 1;//mem
+		r_mem->r_bushandle = hpriv->mmio;
+
+		ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
+		if (ctlr) {
+			ctlr->r_mem = r_mem;
+			ctlr->dev_id = 0; //or 0x90ca104d;
+			ctlr->trace_len = 6;
+			bpcie_sata_phy_init(&pdev->dev, ctlr);
+			kfree(ctlr);
+		}
+		kfree(r_mem);
+	}
+	device_wakeup_enable(&pdev->dev);
+
+	/* save initial config */
+	ahci_save_initial_config(&pdev->dev, hpriv);
+
+	/* prepare host */
+	if (hpriv->cap & HOST_CAP_NCQ) {
+		pi.flags |= ATA_FLAG_NCQ;
+		/*
+		 * Auto-activate optimization is supposed to be
+		 * supported on all AHCI controllers indicating NCQ
+		 * capability, but it seems to be broken on some
+		 * chipsets including NVIDIAs.
+		 */
+		if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
+			pi.flags |= ATA_FLAG_FPDMA_AA;
+
+		/*
+		 * All AHCI controllers should be forward-compatible
+		 * with the new auxiliary field. This code should be
+		 * conditionalized if any buggy AHCI controllers are
+		 * encountered.
+		 */
+		pi.flags |= ATA_FLAG_FPDMA_AUX;
+	}
+
+	if (hpriv->cap & HOST_CAP_PMP)
+		pi.flags |= ATA_FLAG_PMP;
+
+	ahci_set_em_messages(hpriv, &pi);
+
+	/* CAP.NP sometimes indicate the index of the last enabled
+	 * port, at other times, that of the last possible port, so
+	 * determining the maximum port number requires looking at
+	 * both CAP.NP and port_map.
+	 */
+	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+
+	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
+	if (!host) {
+		rc = -ENOMEM;
+		goto unmap_registers;
+	}
+	axhci->host = host;
+	pci_set_drvdata(pdev, axhci);
+
+	host->private_data = hpriv;
+
+	{
+		int index = 1;
+		int irq = (axhci->nr_irqs > 1) ? (pdev->irq + index) : pdev->irq;
+		hpriv->irq = irq;
+	}
+
+	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+		host->flags |= ATA_HOST_PARALLEL_SCAN;
+	else
+		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
+
+	if (pi.flags & ATA_FLAG_EM)
+		ahci_reset_em(host);
+
+	for (i = 0; i < host->n_ports; i++) {
+		struct ata_port *ap = host->ports[i];
+
+		ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
+		ata_port_pbar_desc(ap, ahci_pci_bar,
+				   0x100 + ap->port_no * 0x80, "port");
+
+		/* set enclosure management message type */
+		if (ap->flags & ATA_FLAG_EM)
+			ap->em_message_type = hpriv->em_msg_type;
+
+
+		/* disabled/not-implemented port */
+		if (!(hpriv->port_map & (1 << i)))
+			ap->ops = &ata_dummy_port_ops;
+	}
+
+	rc = ahci_reset_controller(host);
+	dev_dbg(&pdev->dev, "ahci_reset_controller returned %d\n", rc);
+	if (rc)
+		goto release_host;
+
+	ahci_init_controller(host);
+	ahci_print_info(host, "ATA");
+
+	if (!bus_master) {
+		pci_set_master(pdev);
+		bus_master = true;
+	}
+
+	rc = ahci_host_activate(host, &ahci_sht);
+	dev_dbg(&pdev->dev, "ahci_host_activate returned %d\n", rc);
+	if (rc) {
+		goto host_deactivate;
+	}
+
+	pm_runtime_put_noidle(&pdev->dev);
+	return 0;
+
+	host_deactivate:
+	release_host:
+	unmap_registers:
+		iounmap(hpriv->mmio);
+	release_mem_region:
+		devm_release_mem_region(&pdev->dev, rsrc_start, rsrc_len);
+	put_hpriv:
+		//kfree(hpriv);
+		devm_kfree(&pdev->dev, hpriv);
+		dev_err(&pdev->dev, "init %s fail, %d\n",
+				pci_name(pdev), rc);
+	return rc;
+}
+
+static void ahci_remove_one(struct pci_dev *pdev)
+{
+	pm_runtime_get_noresume(&pdev->dev);
+
+	struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+	if (axhci && axhci->host) {
+		ata_host_detach(axhci->host);
+		struct ahci_host_priv *hpriv = axhci->host->private_data;
+		if (hpriv) {
+			iounmap(hpriv->mmio);
+		}
+		axhci->host = NULL;
+	}
+}
+ 
+ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id)
+ {
+@@ -380,9 +370,7 @@ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id
+ 	if (pci_enable_device(dev) < 0)
+ 		return -ENODEV;
+ 
+-	axhci = kzalloc(sizeof(*axhci), GFP_KERNEL);
+-	// TODO (ps4patches): Belize, enable in ahci commit
+-	// axhci = devm_kzalloc(&dev->dev, sizeof(*axhci), GFP_KERNEL);
+	axhci = devm_kzalloc(&dev->dev, sizeof(*axhci), GFP_KERNEL);
+ 	if (!axhci) {
+ 		retval = -ENOMEM;
+ 		goto disable_device;
+@@ -394,21 +382,23 @@ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id
+ 		goto free_axhci;
+ 	}
+ 
+-	// TODO (ps4patches): Belize, disable in ahci commit
+-	pci_set_master(dev);
+	if(dev->device != PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
+		pci_set_master(dev);
+	}
+ 
+ 	if (pci_set_dma_mask(dev, DMA_BIT_MASK(31)) ||
+ 		pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(31))) {
+ 		return -ENODEV;
+ 	}
+ 
+-	// TODO (ps4patches): Belize, enable in ahci commit
+-//	retval = ahci_init_one(dev);
+-//	dev_dbg(&dev->dev, "ahci_init_one returned %d", retval);
+-//	if (!bus_master) {
+-//		pci_set_master(dev);
+-//		bus_master = true;
+-//	}
+	if(dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
+		retval = ahci_init_one(dev);
+		dev_dbg(&dev->dev, "ahci_init_one returned %d", retval);
+		if (!bus_master) {
+			pci_set_master(dev);
+			bus_master = true;
+		}
+	}
+ 
+ 	for (idx = 0; idx < NR_DEVICES; idx++) {
+  		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1){ //this is for Belize and Baikal
+@@ -426,11 +416,12 @@ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id
+ 		xhci_aeolia_remove_one(dev, idx);
+ 	apcie_free_irqs(dev->irq, axhci->nr_irqs);
+ free_axhci:
+-	kfree(axhci);
+	devm_kfree(&dev->dev, axhci);
+ 
+-	// TODO (ps4patches): Belize, disable in ahci commit
+-	// devm_kfree(&dev->dev, axhci);
+-	// pci_set_drvdata(dev, NULL);
+	// TODO (ps4patches): Don't aeolia and baikal also need this?
+	if(dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
+		pci_set_drvdata(dev, NULL);
+	}
+ disable_device:
+ 	pci_disable_device(dev);
+ 	return retval;
+@@ -447,9 +438,8 @@ static void xhci_aeolia_remove(struct pci_dev *dev)
+ 		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+ 			if(idx != 1)
+ 				xhci_aeolia_remove_one(dev, idx);
+-			// TODO (ps4patches): Belize, enable in ahci commit
+-			// else
+-			//	ahci_remove_one(dev);
+			else if (dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI)
+				ahci_remove_one(dev);
+ 		}
+ 		else
+ 			xhci_aeolia_remove_one(dev, idx);
+@@ -463,32 +453,38 @@ static void xhci_aeolia_remove(struct pci_dev *dev)
+ 	pci_disable_device(dev);
+ }
+ 
+-// TODO (ps4patches): Belize, enable in ahci commit
+-//static void xhci_hcd_pci_shutdown(struct pci_dev *dev){
+-//	struct aeolia_xhci *axhci;
+-//	struct usb_hcd		*hcd;
+-//	int idx;
+-//
+-//	axhci = pci_get_drvdata(dev);
+-//	if (!axhci)
+-//		return;
+-//
+-//	for (idx = 0; idx < NR_DEVICES; idx++) {
+-//		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+-//			if(idx != 1) {
+-//				hcd = axhci->hcd[idx];
+-//				if (hcd) {
+-//					if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && hcd->driver->shutdown) {
+-//						hcd->driver->shutdown(hcd);
+-//						if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
+-//							free_irq(hcd->irq, hcd);
+-//					}
+-//				}
+-//			}
+-//		}
+-//	}
+-//}
+static void xhci_hcd_pci_shutdown(struct pci_dev *dev){
+
+	// We want to use the normal shutdown if we aren't belize
+	if (dev->device != PCI_DEVICE_ID_SONY_BELIZE_XHCI)
+	{
+		usb_hcd_pci_shutdown(dev);
+		return;
+	}
+
+	struct aeolia_xhci *axhci;
+	struct usb_hcd	   *hcd;
+	int idx;
+
+	axhci = pci_get_drvdata(dev);
+	if (!axhci)
+		return;
+ 
+	for (idx = 0; idx < NR_DEVICES; idx++) {
+		if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+			if(idx != 1) {
+				hcd = axhci->hcd[idx];
+				if (hcd) {
+					if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && hcd->driver->shutdown) {
+						hcd->driver->shutdown(hcd);
+						if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
+							free_irq(hcd->irq, hcd);
+					}
+				}
+			}
+		}
+	}
+}
+ 
+ static const struct pci_device_id pci_ids[] = {
+ 		{ PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_XHCI) },
+@@ -557,10 +553,7 @@ static struct pci_driver xhci_aeolia_driver = {
+ 	.probe =	xhci_aeolia_probe,
+ 	.remove =	xhci_aeolia_remove,
+ 	/* suspend and resume implemented later */
+-
+-	.shutdown = usb_hcd_pci_shutdown,
+-	// TODO (ps4patches): Belize, enable in ahci commit
+-	//.shutdown = 	xhci_hcd_pci_shutdown,
+	.shutdown = 	xhci_hcd_pci_shutdown,
+ #ifdef CONFIG_PM_SLEEP
+ 	.driver = {
+ 		.pm = &xhci_aeolia_pm_ops
+-- 
+2.45.1
+
@@ -0,0 +1,25 @@
+From f94cfdd446ab433ba0e9a0cb074372025de283eb Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Wed, 29 Dec 2021 16:15:26 +0100
+Subject: [PATCH 16/22] fix: this probably needs to be the amount of interrupts
+
+---
+ drivers/ps4/ps4-apcie.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index fd27a4f38e61..b0bbc3f9891c 100644
+--- a/drivers/ps4/ps4-apcie.c
+++ b/drivers/ps4/ps4-apcie.c
+@@ -343,7 +343,7 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ 	}
+ #endif
+ 
+-	desc = alloc_msi_entry(bare_dev, 1, NULL);
+	desc = alloc_msi_entry(bare_dev, nvec, NULL);
+ 
+ 	info.desc = desc;
+ 	info.data = sc;
+-- 
+2.45.1
+
@@ -0,0 +1,24 @@
+From 62b05b54178ecba3e2d42fbe78b97da94b0fec81 Mon Sep 17 00:00:00 2001
+From: Ps3ita Team <ps3ita-team@ps3ita.it>
+Date: Wed, 13 Feb 2019 14:09:55 +0100
+Subject: [PATCH 17/22] Also on liverpool num_crtc is 6
+
+---
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index aaa6893d8e51..bd9d32217d25 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -404,6 +404,7 @@ static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
+ 	case CHIP_BONAIRE:
+ 	case CHIP_HAWAII:
+ 	case CHIP_GLADIUS:
+	case CHIP_LIVERPOOL:
+ 		num_crtc = 6;
+ 		break;
+ 	case CHIP_KAVERI:
+-- 
+2.45.1
+
@@ -0,0 +1,24 @@
+From 0bf01d7fb8556417ca16ce96b230dd2741de8d48 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Thu, 30 Dec 2021 15:05:26 +0100
+Subject: [PATCH 18/22] fix: cherrypick doubled CHIP_LIVERPOOL
+
+---
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index bd9d32217d25..e54b86bd6d99 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -408,7 +408,6 @@ static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
+ 		num_crtc = 6;
+ 		break;
+ 	case CHIP_KAVERI:
+-	case CHIP_LIVERPOOL:
+ 		num_crtc = 4;
+ 		break;
+ 	case CHIP_KABINI:
+-- 
+2.45.1
+
@@ -0,0 +1,25 @@
+From 4e2075413f8a4232857f9a87905f8afc28e74267 Mon Sep 17 00:00:00 2001
+From: Ps3ita Team <psxitateam@psxita.it>
+Date: Sat, 30 May 2020 12:04:24 +0200
+Subject: [PATCH 19/22] Missing break;
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 8513dd006ad5..3c2e63c2d32b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -4956,7 +4956,7 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ 		adev->gfx.config.max_tile_pipes = 8; // Verified
+ 		adev->gfx.config.max_cu_per_sh = 9; // Probably OK
+ 		adev->gfx.config.max_sh_per_se = 1; // Verified
+-		adev->gfx.config.max_backends_per_se = 1; // Probably OK?
+		adev->gfx.config.max_backends_per_se = 2; // Probably OK?
+ 		adev->gfx.config.max_texture_channel_caches = 4; // ??
+ 		adev->gfx.config.max_gprs = 256;
+ 		adev->gfx.config.max_gs_threads = 32; // ??
+-- 
+2.45.1
+
@@ -0,0 +1,25 @@
+From 9dbe4ba89c9f330e27257ad50b9da4cf9ff1ac9a Mon Sep 17 00:00:00 2001
+From: Rick de Bondt <rick_1996@hotmail.com>
+Date: Fri, 31 Dec 2021 15:19:08 +0100
+Subject: [PATCH 20/22] fix: needed for video codec support
+
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index 353899a95424..147db89444fd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -136,6 +136,8 @@ static int cik_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ 	case CHIP_KAVERI:
+ 	case CHIP_KABINI:
+ 	case CHIP_MULLINS:
+	case CHIP_LIVERPOOL:
+	case CHIP_GLADIUS:
+ 		if (encode)
+ 			*codecs = &cik_video_codecs_encode;
+ 		else
+-- 
+2.45.1
+
@@ -0,0 +1,36 @@
+From dc139fd452cfa78583a695b0d4fc2cdec39b31da Mon Sep 17 00:00:00 2001
+From: crashniels <39709384+crashniels@users.noreply.github.com>
+Date: Fri, 24 May 2024 19:47:37 +0200
+Subject: [PATCH 21/22] fix: gcc newer than 11
+
+https://lore.kernel.org/lkml/20220129010215.781601-1-jforbes@fedoraproject.org/t/
+---
+ tools/lib/subcmd/subcmd-util.h | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/tools/lib/subcmd/subcmd-util.h b/tools/lib/subcmd/subcmd-util.h
+index b2aec04fce8f..7009fc176636 100644
+--- a/tools/lib/subcmd/subcmd-util.h
+++ b/tools/lib/subcmd/subcmd-util.h
+@@ -49,9 +49,15 @@ static NORETURN inline void die(const char *err, ...)
+ 
+ static inline void *xrealloc(void *ptr, size_t size)
+ {
+-	void *ret = realloc(ptr, size);
+-	if (!ret)
+-		die("Out of memory, realloc failed");
+	void *ret;
+	if (!size)
+		size = 1;
+	ret = realloc(ptr, size);
+	if (!ret) {
+		ret = realloc(ptr, size);
+		if (!ret)
+			die("Out of memory, realloc failed");
+	}
+ 	return ret;
+ }
+ 
+-- 
+2.45.1
+
@@ -0,0 +1,39 @@
+From 77961812e981b14669eb51cfa67181149a9bb64a Mon Sep 17 00:00:00 2001
+From: crashniels <39709384+crashniels@users.noreply.github.com>
+Date: Sat, 25 May 2024 19:32:05 +0200
+Subject: [PATCH 22/22] fix: use upstream values
+
+---
+ drivers/usb/host/xhci-aeolia.c | 2 +-
+ drivers/usb/host/xhci.c        | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-aeolia.c b/drivers/usb/host/xhci-aeolia.c
+index 1401af61430c..9ab0be144f42 100644
+--- a/drivers/usb/host/xhci-aeolia.c
+++ b/drivers/usb/host/xhci-aeolia.c
+@@ -43,7 +43,7 @@ static void xhci_aeolia_quirks(struct device *dev, struct xhci_hcd *xhci)
+ 	 * Do not try to enable MSIs, we provide the MSIs ourselves
+ 	 * Do not touch DMA mask, we need a custom one
+ 	 */
+-	xhci->quirks |= XHCI_PLAT | XHCI_PLAT_DMA;
+	xhci->quirks |= XHCI_PLAT | XHCI_SUSPEND_RESUME_CLKS;
+ }
+ 
+ /* called during probe() after chip reset completes */
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 1c8fb48c7095..a79e9dc827e4 100644
+--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
+@@ -5373,7 +5373,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+ 
+ 	/* Set dma_mask and coherent_dma_mask to 64-bits,
+ 	 * if xHC supports 64-bit addressing */
+-	if (!(xhci->quirks & XHCI_PLAT_DMA)) {
+	if (!(xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) {
+ 		if (HCC_64BIT_ADDR(xhci->hcc_params) &&
+ 		    !dma_set_mask(dev, DMA_BIT_MASK(64))) {
+ 			xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+-- 
+2.45.1
+
@@ -0,0 +1,112 @@
+pkgname=linux-sony-ps4
+pkgver=5.15.110
+pkgrel=0
+pkgdesc="Sony Playstation 4 kernel fork"
+arch="x86_64"
+_flavor="sony-ps4"
+_carch="x86"
+url="https://kernel.org"
+license="GPL-2.0-only"
+options="!strip !check !tracedeps
+	pmb:cross-native
+	pmb:kconfigcheck-community
+	"
+makedepends="
+	bash
+	bison
+	elfutils-dev
+	findutils
+	flex
+	linux-headers
+	openssl-dev
+	perl
+	postmarketos-installkernel
+	linux-firmware-mrvl
+"
+
+# Source
+_config="config-$_flavor.$arch"
+case $pkgver in
+	*.*.*)	_kernver=${pkgver%.0};;
+	*.*)	_kernver=$pkgver;;
+esac
+
+source="
+	https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/snapshot/linux-${_kernver//_/-}.tar.gz
+	$_config
+
+	0001-feat-very-basic-platform-support.patch
+	0002-feat-amdgpu-patches.patch
+	0003-feat-radeon-patches.patch
+	0004-feat-temperature-sensors.patch
+	0005-feat-sdhci-support.patch
+	0006-feat-ethernet-support.patch
+	0007-feat-usb-support.patch
+	0008-feat-configuration.patch
+	0009-feat-trying-to-modernize-ps4-apcie-so-it-works-with-.patch
+	0010-feat-working-state-broken-gpu.patch
+	0011-fix-incorrectly-applied-patches-and-missing-patches.patch
+	0012-fix-radeon-drivers.patch
+	0013-fix-amdgpu-drivers.patch
+	0014-fix-re-add-legacy-bridge-functions.patch
+	0015-feat-potentially-added-belize-ahci-support-in-a-univ.patch
+	0016-fix-this-probably-needs-to-be-the-amount-of-interrup.patch
+	0017-Also-on-liverpool-num_crtc-is-6.patch
+	0018-fix-cherrypick-doubled-CHIP_LIVERPOOL.patch
+	0019-Missing-break.patch
+	0020-fix-needed-for-video-codec-support.patch
+	0021-fix-gcc-newer-than-11.patch
+	0022-fix-use-upstream-values.patch
+"
+builddir="$srcdir/linux-${_kernver//_/-}"
+
+prepare() {
+	default_prepare
+	cp "$srcdir/$_config" .config
+}
+
+build() {
+	unset LDFLAGS
+	make ARCH="$_carch" CC="${CC:-gcc}" \
+		KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-$_flavor"
+}
+
+package() {
+	mkdir -p "$pkgdir"/boot
+	make install modules_install \
+		ARCH="$_carch" \
+		INSTALL_PATH="$pkgdir"/boot \
+		INSTALL_MOD_PATH="$pkgdir" \
+		INSTALL_MOD_STRIP=1
+	rm -f "$pkgdir"/lib/modules/*/build "$pkgdir"/lib/modules/*/source
+
+	install -D "$builddir"/include/config/kernel.release \
+		"$pkgdir"/usr/share/kernel/$_flavor/kernel.release
+}
+
+sha512sums="
+405be3edf5855e45b50fd163542e00f58fab0d80c9e93e9605100107eba79ce4b49b83d5ddda3226665bdbdd1c31ac06b4ef05cf87b31f7cf1ff8adf662f2178  linux-5.15.110.tar.gz
+1632c7eb73a7341b8fa1981a66bb59fe21aa6d04cad11bbbf85823950451240d942c40c8eb0b7a1301beec00f3375ae84cbb50594cca4f5fa9983fca56f09dae  config-sony-ps4.x86_64
+7d4e6ab0d273b4d121bfb485334ea949abc4466a914ac596edfae716f3f1d5dde896d27b2b29efd77115d732a0256db3b395ab7cf8d91a47d4a3c45778dc753e  0001-feat-very-basic-platform-support.patch
+e69400cbc1772bc247868004f874c174289747fc36f5df6002664a6813fd24b7fe2dae3b6f6e0647466f89735454914d49316bbb996dd41863bcca1424c5191c  0002-feat-amdgpu-patches.patch
+cffb257874c4e746c82a06be9b9442df9c2deb897e479c7d75a7d73883a64e0d9f00812e1468d8e3fdd15eda0bcfe92668c96bee2f7e2de57c1088f467b329b4  0003-feat-radeon-patches.patch
+262b0934845d9c8bc92c6cacf8cbb1fb697830ac386380c27de586766b801c52ce0230755b62f4abd44c39fc0559446749a212d666636102c35d34299d8cf6c5  0004-feat-temperature-sensors.patch
+536daa2a900ae214a2a1cde277c1ae1b9c4d5a740ddf4a8d2d23e5a4578eeb2e274d89ce917d9705495814580ceceb9cbf69ccb81e14d88ac932f84f1bb4fcad  0005-feat-sdhci-support.patch
+1f960d7bcb8805f2c86e71125a73e28ba8b6b1dcf230a0994ae140f7874ed3e4d8e6ec867d4bff8fdccbfc94b432ccaf6c01e8774a702984f57bd323bf72c208  0006-feat-ethernet-support.patch
+7856b33b05a090009dde83a03ec74044ae64100469ac004c94913a895ccd91c1b7c4623bcc08217e04110a79ef599018a9925c308d8f7e9e89791704675dfc0b  0007-feat-usb-support.patch
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