DO NOT MERGE: apk-tools: workaround apk-tools upgrade failure

see https://gitlab.com/postmarketOS/pmaports/-/issues/3075

.ci/autoupdate.sh

@@ -0,0 +1,111 @@
+#!/bin/sh -e
+# Description: update a list of packages
+# Options: native slow
+# https://postmarketos.org/pmb-ci
+
+if [ "$(id -u)" = 0 ]; then
+	set -x
+	apk add git openssh-keygen grep curl
+	wget "https://gitlab.com/postmarketOS/ci-common/-/raw/master/install_pmbootstrap.sh"
+	sh ./install_pmbootstrap.sh
+	exec su "${TESTUSER:-pmos}" -c "sh -e $0 $*"
+fi
+
+git config --global --add safe.directory "$CI_PROJECT_DIR"
+git config --global user.name "postmarketOS CI"
+# pmaports
+# The email address is the username of the bot (from the GitLab group members page) @noreply.gitlab.com
+git config --global user.email "project_8065375_bot_13cf44ca4cd2c938688af6e3d500d9cb@noreply.gitlab.com"
+
+# For testing with pmaports-autoupdate-test repo
+# git config --global user.email "project_58002231_bot_be2d4e9e7aba929855726aafe12940d6@noreply.gitlab.com"
+
+# Configure SSH key for signing
+mkdir -p ~/.ssh
+cp "$PMAPORTS_SSH_KEY" ~/.ssh/pmaports
+chmod 600 ~/.ssh/pmaports
+# Generate public key from private
+ssh-keygen -t ecdsa -f ~/.ssh/pmaports -y > ~/.ssh/pmaports.pub
+
+git config --global gpg.format ssh
+git config --global user.signingkey ~/.ssh/pmaports.pub
+
+export PYTHONUNBUFFERED=1
+
+PKGS="$1"
+if [ -z "$PKGS" ]; then
+	echo "Usage: $0 <packages>"
+	exit 1
+fi
+echo "Checking for new versions of packages: $PKGS"
+
+update_linux_next() {
+	# Check for the latest -next tag
+	local latest
+	local pkgver
+	local new_pkgver
+
+	# Get the current version
+	# shellcheck source=/dev/null
+	pkgver=$(. device/testing/linux-next/APKBUILD; echo "$pkgver")
+
+	curl -s "https://gitlab.com/linux-kernel/linux-next/-/tags?format=atom" | grep -oP "(?<=<title>)[^<]+" | tail -n +2 > /tmp/tags
+
+	latest=$(grep -v "v" < /tmp/tags | head -n1)
+	if [ -z "$latest" ]; then
+		echo "Failed to get the latest -next tag"
+		exit 1
+	fi
+	echo "Latest -next tag: $latest"
+
+	new_pkgver=$(grep "v" < /tmp/tags | head -n1)
+	if [ -z "$new_pkgver" ]; then
+		echo "Failed to get the latest mainline tag from atom feed, reusing current pkgver"
+		new_pkgver="${pkgver%_git*}"
+	else
+		echo "Latest mainline tag: $new_pkgver"
+		# new_pkgver is like 'v6.9-rc1' but we want '6.9'
+		new_pkgver=$(echo "$new_pkgver" | sed -e 's/^v//' -e 's/-.*//')
+	fi
+
+	new_pkgver="${new_pkgver}_git${latest#*-}"
+
+	if [ "$pkgver" = "$new_pkgver" ]; then
+		echo "No new version of linux-next"
+		exit 0
+	fi
+
+	echo "Updating linux-next from $pkgver to $new_pkgver..."
+	sed -i -e "s/pkgver=$pkgver/pkgver=$new_pkgver/" device/testing/linux-next/APKBUILD
+
+	# Update the checksums
+	pmbootstrap checksum linux-next
+
+	# Ensure it builds
+	pmbootstrap --details-to-stdout build linux-next
+
+	# Commit
+	git add device/testing/linux-next/APKBUILD
+	git commit -S -m "linux-next: upgrade to $latest"
+}
+
+# For testing
+#git remote add gitlab https://pmos-ci:"$PMAPORTS_PUSH_TOKEN"@gitlab.com/postmarketOS/pmaports-autoupdate-test.git
+
+git remote add gitlab https://pmos-ci:"$PMAPORTS_PUSH_TOKEN"@gitlab.com/postmarketOS/pmaports.git
+git fetch gitlab
+git checkout --track gitlab/master
+
+for pkg in $PKGS; do
+	case "$pkg" in
+		linux-next)
+			update_linux_next
+			;;
+		*)
+			echo "Unknown package: $pkg"
+			exit 1
+			;;
+	esac
+done
+
+git push

.ci/grep.sh

@@ -80,4 +80,11 @@ if grep -q 'before wpa_supplicant' $OPENRC_SERVICE_FILES; then
 	exit_code=1
 fi
 
+if grep -qEr 'PMOS_NO_OUTPUT_REDIRECT' -- *; then
+	echo "ERROR: PMOS_NO_OUTPUT_REDIRECT is deprecated and doesn't do anything."
+	echo "Please remove it from the following files:"
+	grep --color=always -Er 'PMOS_NO_OUTPUT_REDIRECT' -- *
+	exit_code=1
+fi
+
 exit "$exit_code"

.ci/kconfig.sh

@@ -6,6 +6,7 @@
 
 if [ "$(id -u)" = 0 ]; then
 	set -x
+	export PMBOOTSTRAP_TAG=master
 	wget "https://gitlab.com/postmarketOS/ci-common/-/raw/master/install_pmbootstrap.sh"
 	sh ./install_pmbootstrap.sh
 	exec su "${TESTUSER:-pmos}" -c "sh -e $0"

.ci/lib/build_changed_aports.py

@@ -15,6 +15,9 @@ import pmb.helpers.pmaports
 
 def build_strict(packages, arch):
     common.run_pmbootstrap(["build_init"])
+    common.run_pmbootstrap(["config", "mirrors_postmarketos",
+                            "http://mirror.postmarketos.org/postmarketos/staging/systemd/"])
+    common.run_pmbootstrap(["config", "systemd", "always"])
     common.run_pmbootstrap(["--details-to-stdout", "--no-ccache", "build",
                             "--strict", "--force",
                             "--arch", arch, ] + list(packages))

.ci/lib/check_changed_kernels.py

@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright 2023 Oliver Smith
+# Copyright 2024 Oliver Smith
 # SPDX-License-Identifier: GPL-3.0-or-later
 
 import glob
@@ -10,42 +10,30 @@ import subprocess
 # Same dir
 import common
 
-# pmbootstrap
-import add_pmbootstrap_to_import_path  # noqa
-import pmb.parse
-import pmb.helpers.logging
 
-
-def check_kconfig(args, pkgnames):
+def check_kconfig(pkgnames):
     last_failed = None
     for i in range(len(pkgnames)):
         pkgname = pkgnames[i]
         print(f"  ({i+1}/{len(pkgnames)}) {pkgname}")
 
-        apkbuild_path = pmb.helpers.pmaports.find(args, pkgname)
-        apkbuild = pmb.parse._apkbuild.apkbuild(f"{apkbuild_path}/APKBUILD")
+        p = subprocess.run(["pmbootstrap", "kconfig", "check", "--keep-going", pkgname],
+                           check=False)
 
-        options = []
-
-        for opt in apkbuild["options"]:
-            if "pmb:kconfigcheck" in opt:
-                options += [opt]
-
-        if len(options):
-            options.sort()
-            print(f'options="{" ".join(options)}"')
-
-        if "!pmb:kconfigcheck" in apkbuild["options"]:
-            print("skipped (!pmb:kconfigcheck)")
-            continue
-
-        if not pmb.parse.kconfig.check(args, pkgname, details=True):
+        if p.returncode:
             last_failed = pkgname
 
     return last_failed
 
 
+def check_kconfig_all():
+    p = subprocess.run(["pmbootstrap", "kconfig", "check", "--keep-going"], check=False)
+    return p.returncode == 0
+
+
 def show_error(last_failed):
+    print("")
+    print("---")
     print("")
     print("Please adjust your kernel config. This is required for getting your"
           " patch merged.")
@@ -59,10 +47,43 @@ def show_error(last_failed):
     print("Run this check again (on all kernels you modified):")
     print("  pmbootstrap ci kconfig")
     print("")
+    print("---")
+    print("")
+
+
+def show_error_all():
+    print("")
+    print("---")
+    print("")
+    print("Please adjust the failed kernel configs. This is required for")
+    print("getting your patch merged.")
+    print("")
+    print("If a kernel in the testing category failed, and fixing is too much")
+    print("effort, remove 'pmb:kconfigcheck-community' from the APKBUILD.")
+    print("")
+    print("Edit a kernel config:")
+    print("  pmbootstrap kconfig edit <PACKAGE NAME>")
+    print("")
+    print("Test a specific kernel config again:")
+    print("  pmbootstrap kconfig check <PACKAGE NAME>")
+    print("")
+    print("Run this check again (on all kernels you modified):")
+    print("  pmbootstrap ci kconfig")
+    print("")
+    print("---")
+    print("")
 
 
 if __name__ == "__main__":
     common.add_upstream_git_remote()
+
+    if "kconfigcheck.toml" in common.get_changed_files():
+        print("kconfigcheck.toml changed -> checking all kernels")
+        if not check_kconfig_all():
+            show_error_all()
+            exit(1)
+        exit(0)
+
     pkgnames = common.get_changed_kernels()
     print(f"Changed kernels: {pkgnames}")
 
@@ -70,13 +91,7 @@ if __name__ == "__main__":
         print("No kernels changed in this branch")
         exit(0)
 
-    # Initialize args (so we can use pmbootstrap's kconfig parsing)
-    sys.argv = ["pmbootstrap", "kconfig", "check"]
-    args = pmb.parse.arguments()
-    pmb.helpers.logging.init(args)
-
-    print("Running kconfig check on changed kernels...")
-    last_failed = check_kconfig(args, pkgnames)
+    last_failed = check_kconfig(pkgnames)
 
     if last_failed:
         show_error(last_failed)

.ci/lib/common.py

@@ -60,34 +60,8 @@ def get_upstream_branch():
 
         :returns: branch name, e.g. "v20.05" """
 
-    # Prefer gitlab CI target branch name if it's set (i.e. running in gitlab CI)
-    if target_branch := os.environ.get("CI_MERGE_REQUEST_TARGET_BRANCH_NAME"):
-        return target_branch
-
-    global cache
-    if "upstream_branch" in cache:
-        return cache["upstream_branch"]
-
-    # Get channel (e.g. "stable") from pmaports.cfg
-    # https://postmarketos.org/pmaports.cfg
-    pmaports_dir = get_pmaports_dir()
-    pmaports_cfg = configparser.ConfigParser()
-    pmaports_cfg.read(f"{pmaports_dir}/pmaports.cfg")
-    channel = pmaports_cfg["pmaports"]["channel"]
-
-    # Get branch_pmaports (e.g. "v20.05") from channels.cfg
-    # https://postmarketos.org/channels.cfg
-    channels_cfg_str = run_git(["show", "upstream/master:channels.cfg"])
-    channels_cfg = configparser.ConfigParser()
-    channels_cfg.read_string(channels_cfg_str)
-    assert channel in channels_cfg, \
-        f"Channel '{channel}' from pmaports.cfg in your branch is unknown." \
-        " This appears to be an old branch, consider recreating your change" \
-        " on top of master."
-
-    ret = channels_cfg[channel]["branch_pmaports"]
-    cache["upstream_branch"] = ret
-    return ret
+    # HACK for master_staging_systemd branch
+    return "master_staging_systemd"
 
 
 def get_changed_files(removed=True):

.ci/testcases/test_directory_structure.py

@@ -10,6 +10,7 @@ expected_directories = [
     "device/community",
     "device/main",
     "device/testing",
+    "extra-repos/systemd",
     "main",
     "modem",
     "non-free",

.ci/testcases/test_kernel.py

@@ -22,6 +22,9 @@ def test_aports_kernel(args):
         apkbuild = pmb.parse.apkbuild(path)
         aport_name = os.path.basename(os.path.dirname(path))
 
+        if aport_name == "linux-pam":
+            continue  # This package isn't a linux kernel!
+
         if "pmb:cross-native" not in apkbuild["options"]:
             raise RuntimeError(f"{aport_name}: \"pmb:cross-native\" missing in"
                                " options= line")

.editorconfig

@@ -12,3 +12,8 @@ indent_style = tab
 end_of_line = lf
 trim_trailing_whitespace = true
 insert_final_newline = true
+
+# Forked from Alpine
+[extra-repos/systemd/networkmanager/networkmanager.rules]
+indent_style = space
+indent_size = 4

.gitlab-ci.yml

@@ -9,6 +9,7 @@ after_script:
 stages:
   - lint
   - build
+  - autoupdate
 
 # This defines the rules for when a pipeline should run.
 workflow:
@@ -18,8 +19,8 @@ workflow:
       when: never
     # Run for merge requests
     - if: $CI_PIPELINE_SOURCE == "merge_request_event"
-    # Run scheduled pipeline for autoupdate
-    - if: $CI_PIPELINE_SOURCE == "schedule"
+    # Run scheduled pipeline for autoupdate or manually triggered pipeline
+    - if: $CI_PIPELINE_SOURCE == "schedule" || $CI_PIPELINE_SOURCE == "web"
 
 # device documentation
 wiki:
@@ -101,6 +102,7 @@ kernel-kconfig:
   rules:
     - if: $CI_PIPELINE_SOURCE == "merge_request_event" || $CI_COMMIT_REF_PROTECTED == "false"
       changes:
+        - kconfigcheck.toml
         - device/*/linux-*/config-*
         - main/linux-*/config-*
   script:
@@ -123,6 +125,8 @@ mr-settings:
 # build changed aports
 .build:
   stage: build
+  tags:
+    - saas-linux-large-amd64
   rules:
     - if: $CI_PIPELINE_SOURCE == "merge_request_event" || $CI_COMMIT_REF_PROTECTED == "false"
   before_script:
@@ -141,13 +145,10 @@ build-x86_64:
   script:
     - .ci/build-x86_64.sh
 
-build-x86:
-  extends: .build
-  script:
-    - .ci/build-x86.sh
-
 build-aarch64:
   extends: .build
+  tags:
+    - saas-linux-large-arm64
   script:
     - .ci/build-aarch64.sh
 
@@ -156,12 +157,24 @@ build-armv7:
   script:
     - .ci/build-armv7.sh
 
-build-armhf:
-  extends: .build
+auto-update:
+  stage: autoupdate
+  # We build packages before merging too
+  tags:
+    - saas-linux-large-amd64
+  rules:
+    # This variable is set in the scheduled pipeline configuration. It should be a space separated list of
+    # package names to update.
+    - if: $AUTOUPDATE_PACKAGES != null && $CI_PIPELINE_SOURCE == "schedule" || $CI_PIPELINE_SOURCE == "web"
+  before_script:
+    - .ci/lib/gitlab_prepare_ci.sh
   script:
-    - .ci/build-armhf.sh
-
-build-riscv64:
-  extends: .build
-  script:
-    - .ci/build-riscv64.sh
+    - .ci/autoupdate.sh "$AUTOUPDATE_PACKAGES"
+  after_script:
+    - .ci/lib/move_logs.sh $CI_PROJECT_DIR
+  artifacts:
+    when: on_failure
+    paths:
+      - log.txt
+      - log_testsuite_pmaports.txt
+      - pmbootstrap.cfg

.gitlab/issue_templates/Default.md

@@ -28,7 +28,6 @@
 -->
 * [ ] edge (`master` branch)
 * [ ] `v24.06`
-* [ ] `v23.12` (supported until 2024-07-16)
 
 * [ ] I confirm that the issue still is present after running `sudo apk upgrade -a`
 
@@ -51,4 +50,13 @@
 -->
 
 ### Additional information
-<!-- logs, etc. -- make use <details> for long listings -->
+<!--
+	logs, etc. -- make use <details> for long listings
+
+	If your device displays an error message on boot or drops to the debug
+	shell, attaching it to your PC with a USB cable may show a removable USB
+	drive. You can drag and drop the .tar.gz file or otherwise upload it
+	here.
+
+	Refer to the README file on the device for more information.
+-->

CODEOWNERS

@@ -72,6 +72,8 @@ device/*/device-nvidia-tegra-armv7/		@clamor-s @okias @mschwalm @nokun
 device/*/device-odroid-xu4/			@Grimler
 device/*/device-oneplus-enchilada/		@calebccff
 device/*/device-oneplus-fajita/			@calebccff
+device/*/device-postmarketos-trailblazer/	@calebccff
+device/*/device-qcom-msm8909/			@wonderfulShrineMaidenOfParadise
 device/*/device-qemu-aarch64/			@Minecrell @ollieparanoid
 device/*/device-qemu-amd64/			@Minecrell @ollieparanoid
 device/*/device-qemu-riscv64/			@Minecrell @z3ntu
@@ -92,9 +94,10 @@ device/*/kobo-epdc-extractor/			@akemnade
 device/*/linux-google-nyan/			@jenneron
 device/*/linux-google-veyron/			@jenneron
 device/*/linux-huawei-plank/			@gtrxAC
+device/*/linux-next/				@calebccff
 device/*/linux-postmarketos-allwinner/		@Arnavion @PsychoGame
 device/*/linux-postmarketos-amlogic/		@funderscore @exkc
-device/*/linux-postmarketos-exynos4/		@Newbyte @ThiagaoPlusPlus
+device/*/linux-postmarketos-exynos4/		@Newbyte @Grimler @knuxify
 device/*/linux-postmarketos-exynos5/		@jenneron @Grimler
 device/*/linux-postmarketos-grate/		@clamor-s @jenneron @jethrob
 device/*/linux-postmarketos-imx-ereader/	@akemnade
@@ -113,6 +116,7 @@ device/*/linux-samsung-j5y17lte/	@andrisas
 device/*/linux-samsung-klimtlte/		@Grimler
 device/*/oem-amd/				@craftyguy
 device/*/oem-intel/				@craftyguy
+device/*/oem-nvidia/				@craftyguy
 device/*/soc-mediatek-mt8183/			@jenneron
 device/*/soc-qcom-msm8953/			@barni2000
 device/*/soc-qcom-msm8996/			@Tooniis
@@ -125,6 +129,7 @@ device/*/u-boot-pinephone/			@Arnavion @PsychoGame
 device/*/wl1251-cal/				@Danct12
 main/postmarketos*gnome*/			@pabloyoyoista @Newbyte
 main/postmarketos-initramfs/			@calebccff @craftyguy
+main/postmarketos-ui-i3wm/			@fossdd
 main/postmarketos-ui-phosh/			@pabloyoyoista @Newbyte
 main/postmarketos-ui-plasma-mobile/		@PureTryOut
 main/shutdown-clear-rtc-wakealarm/		@Arnavion

channels.cfg

@@ -15,7 +15,7 @@ branch_aports=3.20-stable
 mirrordir_alpine=v3.20
 
 [v23.12]
-description=Old release (supported until 2024-07-16)
+description=Old release (unsupported)
 branch_pmaports=v23.12
 branch_aports=3.19-stable
 mirrordir_alpine=v3.19

cross/busybox-static-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-aarch64
 pkgver=1.36.1
-pkgrel=29
+pkgrel=31
 
 _arch="aarch64"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-3dd0da90cf278055d2c9e7710bb0389a5af74c0cabd9d786f4244ca4e36872dd307f8ff8a206479714d445fae903b2aa3292279ad737387d0584c7d34d98a274  busybox-static-1.36.1-r29-aarch64-edge.apk
+c34906bb0a5d7e268ab43ca1e3e2f9c75c06f3f5de8d41671396bcd7d585a79a66e25ad43e80a3e107a1de0ecaf83ac7198163d3e775edbd6d626ef014307ec5  busybox-static-1.36.1-r31-aarch64-edge.apk
 "

cross/busybox-static-armhf/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armhf
 pkgver=1.36.1
-pkgrel=29
+pkgrel=31
 
 _arch="armhf"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-3ed54a2b4c23a08dc066b585198fe81d39b5fd0d54347d9ab727d6bea73cfc4ad9a5fb55c25a3e59ef8fce6cc83a24f0807980f6d3ea6c05029522627192e716  busybox-static-1.36.1-r29-armhf-edge.apk
+7e6a961a0adcbc2912f5b261ce84a62b9189dce49c5dd3d2bcbdae407645dec72c27af8804c1d5446d50e78ea938a4d812c477db199ed83cac7c647c4b41f3fe  busybox-static-1.36.1-r31-armhf-edge.apk
 "

cross/busybox-static-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armv7
 pkgver=1.36.1
-pkgrel=29
+pkgrel=31
 
 _arch="armv7"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-3b2124f93cd873440797b25b5c2456dfc441ff18831ae8a0540bd5ca67f3869766aa6a76e31b9f9d0a7382e760b0d8acb1e91599c65a72298fffbbd4aafc6175  busybox-static-1.36.1-r29-armv7-edge.apk
+b9736dc7df4230196bf05de3bd76b61fc689c56861bc7c5194cd310e23f513cec649c1b3e3f338266b8d58540468d97e8525948a3efc2d1af53e288cd525e836  busybox-static-1.36.1-r31-armv7-edge.apk
 "

cross/gcc-aarch64/0002-gcc-poison-system-directories.patch

@@ -150,13 +150,13 @@ diff --git a/gcc/gcc.cc b/gcc/gcc.cc
 index 16bb07f2cdc..33b56e721d2 100644
 --- a/gcc/gcc.cc
 +++ b/gcc/gcc.cc
-@@ -1146,6 +1146,8 @@ proper position among the other output files.  */
-    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+@@ -1177,6 +1187,8 @@ proper position among the other output files.  */
+    "-z now " \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
 +    %{Wno-poison-system-directories:--no-poison-system-directories} \
 +    %{Werror=poison-system-directories:--error-poison-system-directories} \
-     %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
+     %{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
 diff --git a/gcc/incpath.cc b/gcc/incpath.cc

cross/gcc-aarch64/0013-nopie.patch

@@ -9,23 +9,22 @@ Subject: [PATCH 13/35] nopie
  2 files changed, 40 insertions(+)
 
 diff --git a/gcc/configure b/gcc/configure
-index 8c46369f73f..e59cbee1767 100755
+index 23da7d55d..f38732bb2 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -32268,6 +32268,33 @@ fi
+@@ -34534,6 +34534,29 @@ rm -f core conftest.err conftest.$ac_objext \
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie" >&5
  $as_echo "$gcc_cv_no_pie" >&6; }
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
++# Check if -nopie works.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
 +$as_echo_n "checking for -nopie option... " >&6; }
-+if test "${gcc_cv_nopie+set}" = set; then :
++if ${gcc_cv_nopie+:} false; then :
 +  $as_echo_n "(cached) " >&6
 +else
 +  saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++   LDFLAGS="$LDFLAGS -nopie"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 +/* end confdefs.h.  */
 +int main(void) {return 0;}
 +_ACEOF
@@ -36,40 +35,51 @@ index 8c46369f73f..e59cbee1767 100755
 +fi
 +rm -f core conftest.err conftest.$ac_objext \
 +    conftest$ac_exeext conftest.$ac_ext
-+     LDFLAGS="$saved_LDFLAGS"
++   LDFLAGS="$saved_LDFLAGS"
 +fi
 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_nopie" >&5
 +$as_echo "$gcc_cv_nopie" >&6; }
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
+ 
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -34551,6 +34574,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
  fi
- 
- 
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 5504bf6eb01..57268319de1 100644
+index d7cf0b92c..db2e2c802 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7552,6 +7552,19 @@ AC_CACHE_CHECK([for -no-pie option],
+@@ -7781,6 +7781,15 @@ AC_CACHE_CHECK([for -no-pie option],
+      [gcc_cv_no_pie=yes],
+      [gcc_cv_no_pie=no])
     LDFLAGS="$saved_LDFLAGS"])
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  AC_CACHE_CHECK([for -nopie option],
-+    [gcc_cv_nopie],
-+    [saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     AC_LINK_IFELSE([int main(void) {return 0;}],
-+       [gcc_cv_nopie=yes],
-+       [gcc_cv_nopie=no])
-+     LDFLAGS="$saved_LDFLAGS"])
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
- fi
- AC_SUBST([NO_PIE_FLAG])
++# Check if -nopie works.
++AC_CACHE_CHECK([for -nopie option],
++  [gcc_cv_nopie],
++  [saved_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -nopie"
++   AC_LINK_IFELSE([AC_LANG_SOURCE([int main(void) {return 0;}])],
++     [gcc_cv_nopie=yes],
++     [gcc_cv_nopie=no])
++   LDFLAGS="$saved_LDFLAGS"])
  
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -7798,6 +7807,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
+ fi
 -- 
 2.41.0
 

cross/gcc-aarch64/0023-riscv-disable-multilib-support.patch

@@ -46,10 +46,10 @@ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index f8c2c351e5a..8d9881eadeb 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
-@@ -61,11 +61,3 @@ along with GCC; see the file COPYING3.  If not see
-     %{static:-static}}"
- 
- #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+@@ -60,11 +60,3 @@ along with GCC; see the file COPYING3.  If not see
+ 	%{rdynamic:-export-dynamic} \
+ 	-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
 -
 -#define STARTFILE_PREFIX_SPEC 			\
 -   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\

cross/gcc-aarch64/0026-ada-musl-support-fixes.patch

@@ -41,6 +41,15 @@ index 96306f8cc9a..090b6770ae5 100644
    LIBGNAT_TARGET_PAIRS = \
    a-intnam.ads<libgnarl/a-intnam__linux.ads \
    s-inmaop.adb<libgnarl/s-inmaop__posix.adb \
+@@ -2311,7 +2311,7 @@ ifeq ($(strip $(filter-out aarch64% linux%,$(target_cpu) $(target_os))),)
+   s-intman.adb<libgnarl/s-intman__posix.adb \
+   s-linux.ads<libgnarl/s-linux.ads \
+   $(TRASYM_DWARF_UNIX_PAIRS) \
+-  s-tsmona.adb<libgnat/s-tsmona__linux.adb \
++  s-tsmona.adb<libgnat/s-tsmona.adb \
+   s-mudido.adb<libgnarl/s-mudido__affinity.adb \
+   s-osinte.ads<libgnarl/s-osinte__linux.ads \
+   s-osinte.adb<libgnarl/s-osinte__posix.adb \
 @@ -2420,7 +2420,7 @@ ifeq ($(strip $(filter-out %ia64 linux%,$(target_cpu) $(target_os))),)
    s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \
    s-taspri.ads<libgnarl/s-taspri__posix-noaltstack.ads \

cross/gcc-aarch64/0035-loongarch-disable-multilib-support.patch

@@ -0,0 +1,32 @@
+From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 7 Aug 2023 15:25:58 +0800
+Subject: [PATCH] loongarch disable multilib support
+
+Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
+---
+ gcc/config/loongarch/t-linux    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 23e1fb979..c2753abb8 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -21,11 +21,6 @@ MULTIOSDIR_lp64f := ../lib64/f32$(call if_multiarch,:loongarch64-linux-gnuf32)
+ MULTIOSDIR_lp64s := ../lib64/sf$(call if_multiarch,:loongarch64-linux-gnusf)
+ 
+ # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
+-ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+-
+-    MULTILIB_OSDIRNAMES = .=$(MULTIOSDIR_$(mlib_default))
+-    MULTILIB_OSDIRNAMES += mabi.lp64d=$(MULTIOSDIR_lp64d)
+-    MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+-    MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+-
+-endif
++    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
+-- 
+2.41.0
+

cross/gcc-aarch64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-aarch64/0037-loongarch-disable-multilib-support.patch

@@ -1,61 +0,0 @@
-From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
-From: Jingyun Hua <huajingyun@loongson.cn>
-Date: Mon, 7 Aug 2023 15:25:58 +0800
-Subject: [PATCH] loongarch disable multilib support
-
-Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
----
- gcc/config/loongarch/linux.h    | 10 +---------
- gcc/config/loongarch/t-linux    | 18 +++---------------
- 3 files changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
-index 9059d2441..23eaff0cc 100644
---- a/gcc/config/loongarch/linux.h
-+++ b/gcc/config/loongarch/linux.h
-@@ -22,15 +22,7 @@ along with GCC; see the file COPYING3.  If not see
-  * can work in a multilib environment.  */
- 
- #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
--
--  #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
--    #define ABI_LIBDIR "lib64"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
--    #define ABI_LIBDIR "lib64/f32"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64S
--    #define ABI_LIBDIR "lib64/sf"
--  #endif
--
-+    #define ABI_LIBDIR "lib"
- #endif
- 
- #ifndef ABI_LIBDIR
-diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
-index e40da1792..f72c6e878 100644
---- a/gcc/config/loongarch/t-linux
-+++ b/gcc/config/loongarch/t-linux
-@@ -36,18 +36,6 @@ else
- endif
- 
- # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
--ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
--
--    MULTILIB_OSDIRNAMES = \
--      mabi.lp64d=../lib64$\
--      $(call if_multiarch,:loongarch64-linux-gnu)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64f=../lib64/f32$\
--      $(call if_multiarch,:loongarch64-linux-gnuf32)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64s=../lib64/sf$\
--      $(call if_multiarch,:loongarch64-linux-gnusf)
--
--endif
-+    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
--- 
-2.41.0
-

cross/gcc-aarch64/APKBUILD

@@ -24,7 +24,7 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-aarch64
-pkgver=13.2.1_git20240309
+pkgver=14.2.0
 # i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-aarch64
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for aarch64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -171,7 +171,7 @@ esac
 # currently on x86, x86_64 and ia64
 _libquadmath=$LANG_FORTRAN
 case "$CTARGET_ARCH" in
-x86 | x86_64 | ppc64le)	_libquadmath=$LANG_FORTRAN ;;
+x86 | x86_64)	_libquadmath=$LANG_FORTRAN ;;
 *)		_libquadmath=false ;;
 esac
 
@@ -241,7 +241,8 @@ makedepends="$makedepends_build $makedepends_host"
 #
 # PLEASE submit all patches to gcc to https://gitlab.alpinelinux.org/kaniini/alpine-gcc-patches,
 # so that they can be properly tracked and easily rebased if needed.
-source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+#source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkgbase:-$pkgver}.tar.xz
 	0001-posix_memalign.patch
 	0002-gcc-poison-system-directories.patch
 	0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -276,8 +277,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-	0037-loongarch-disable-multilib-support.patch
+	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -285,7 +286,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 #     - CVE-2023-4039
 
 # we build out-of-tree
-_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+#_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+_gccdir="$srcdir"/gcc-${_pkgbase:-$pkgver}
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 _gcclibexec="/usr/libexec/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 
@@ -364,7 +366,14 @@ build() {
 	$_libgomp	|| _bootstrap_configure="$_bootstrap_configure --disable-libgomp"
 	$_libatomic	|| _bootstrap_configure="$_bootstrap_configure --disable-libatomic"
 	$_libitm	|| _bootstrap_configure="$_bootstrap_configure --disable-libitm"
-	$_libquadmath	|| _arch_configure="$_arch_configure --disable-libquadmath"
+	if ! $_libquadmath; then
+		_arch_configure="$_arch_configure --disable-libquadmath"
+		# ppc64le needs both --disable-libquadmath{,-support}
+		# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116007
+		[ "$CARCH" = "ppc64le" ] &&
+			_arch_configure="$_arch_configure
+				--disable-libquadmath-support"
+	fi
 
 	msg "Building the following:"
 	echo ""
@@ -793,9 +802,9 @@ gdb() {
 }
 
 sha512sums="
-2d1e0374ebdee526f0549319fc9c364968c52a0d4aaa16759f00453cb083fe58d8f463c47d97f3bb74a0a92e251989eb75a50ee5800b4569978c72d25446b44e  gcc-13-20240309.tar.xz
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 720a4001f9a1fa4122e456077ecff8d3eb8af7c83d0a81f9da6a6cca05b23664206a82a349e34482c48bfe40e99aa5f21567613d0913f6a24f282bc84a994496  0028-configure-fix-detection-of-atomic-builtins-in-libato.patch
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@@ -828,6 +837,6 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
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+65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-aarch64/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-armhf/0002-gcc-poison-system-directories.patch

@@ -150,13 +150,13 @@ diff --git a/gcc/gcc.cc b/gcc/gcc.cc
 index 16bb07f2cdc..33b56e721d2 100644
 --- a/gcc/gcc.cc
 +++ b/gcc/gcc.cc
-@@ -1146,6 +1146,8 @@ proper position among the other output files.  */
-    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+@@ -1177,6 +1187,8 @@ proper position among the other output files.  */
+    "-z now " \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
 +    %{Wno-poison-system-directories:--no-poison-system-directories} \
 +    %{Werror=poison-system-directories:--error-poison-system-directories} \
-     %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
+     %{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
 diff --git a/gcc/incpath.cc b/gcc/incpath.cc

cross/gcc-armhf/0013-nopie.patch

@@ -9,23 +9,22 @@ Subject: [PATCH 13/35] nopie
  2 files changed, 40 insertions(+)
 
 diff --git a/gcc/configure b/gcc/configure
-index 8c46369f73f..e59cbee1767 100755
+index 23da7d55d..f38732bb2 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -32268,6 +32268,33 @@ fi
+@@ -34534,6 +34534,29 @@ rm -f core conftest.err conftest.$ac_objext \
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie" >&5
  $as_echo "$gcc_cv_no_pie" >&6; }
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
++# Check if -nopie works.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
 +$as_echo_n "checking for -nopie option... " >&6; }
-+if test "${gcc_cv_nopie+set}" = set; then :
++if ${gcc_cv_nopie+:} false; then :
 +  $as_echo_n "(cached) " >&6
 +else
 +  saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++   LDFLAGS="$LDFLAGS -nopie"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 +/* end confdefs.h.  */
 +int main(void) {return 0;}
 +_ACEOF
@@ -36,40 +35,51 @@ index 8c46369f73f..e59cbee1767 100755
 +fi
 +rm -f core conftest.err conftest.$ac_objext \
 +    conftest$ac_exeext conftest.$ac_ext
-+     LDFLAGS="$saved_LDFLAGS"
++   LDFLAGS="$saved_LDFLAGS"
 +fi
 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_nopie" >&5
 +$as_echo "$gcc_cv_nopie" >&6; }
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
+ 
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -34551,6 +34574,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
  fi
- 
- 
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 5504bf6eb01..57268319de1 100644
+index d7cf0b92c..db2e2c802 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7552,6 +7552,19 @@ AC_CACHE_CHECK([for -no-pie option],
+@@ -7781,6 +7781,15 @@ AC_CACHE_CHECK([for -no-pie option],
+      [gcc_cv_no_pie=yes],
+      [gcc_cv_no_pie=no])
     LDFLAGS="$saved_LDFLAGS"])
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  AC_CACHE_CHECK([for -nopie option],
-+    [gcc_cv_nopie],
-+    [saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     AC_LINK_IFELSE([int main(void) {return 0;}],
-+       [gcc_cv_nopie=yes],
-+       [gcc_cv_nopie=no])
-+     LDFLAGS="$saved_LDFLAGS"])
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
- fi
- AC_SUBST([NO_PIE_FLAG])
++# Check if -nopie works.
++AC_CACHE_CHECK([for -nopie option],
++  [gcc_cv_nopie],
++  [saved_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -nopie"
++   AC_LINK_IFELSE([AC_LANG_SOURCE([int main(void) {return 0;}])],
++     [gcc_cv_nopie=yes],
++     [gcc_cv_nopie=no])
++   LDFLAGS="$saved_LDFLAGS"])
  
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -7798,6 +7807,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
+ fi
 -- 
 2.41.0
 

cross/gcc-armhf/0023-riscv-disable-multilib-support.patch

@@ -46,10 +46,10 @@ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index f8c2c351e5a..8d9881eadeb 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
-@@ -61,11 +61,3 @@ along with GCC; see the file COPYING3.  If not see
-     %{static:-static}}"
- 
- #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+@@ -60,11 +60,3 @@ along with GCC; see the file COPYING3.  If not see
+ 	%{rdynamic:-export-dynamic} \
+ 	-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
 -
 -#define STARTFILE_PREFIX_SPEC 			\
 -   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\

cross/gcc-armhf/0026-ada-musl-support-fixes.patch

@@ -41,6 +41,15 @@ index 96306f8cc9a..090b6770ae5 100644
    LIBGNAT_TARGET_PAIRS = \
    a-intnam.ads<libgnarl/a-intnam__linux.ads \
    s-inmaop.adb<libgnarl/s-inmaop__posix.adb \
+@@ -2311,7 +2311,7 @@ ifeq ($(strip $(filter-out aarch64% linux%,$(target_cpu) $(target_os))),)
+   s-intman.adb<libgnarl/s-intman__posix.adb \
+   s-linux.ads<libgnarl/s-linux.ads \
+   $(TRASYM_DWARF_UNIX_PAIRS) \
+-  s-tsmona.adb<libgnat/s-tsmona__linux.adb \
++  s-tsmona.adb<libgnat/s-tsmona.adb \
+   s-mudido.adb<libgnarl/s-mudido__affinity.adb \
+   s-osinte.ads<libgnarl/s-osinte__linux.ads \
+   s-osinte.adb<libgnarl/s-osinte__posix.adb \
 @@ -2420,7 +2420,7 @@ ifeq ($(strip $(filter-out %ia64 linux%,$(target_cpu) $(target_os))),)
    s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \
    s-taspri.ads<libgnarl/s-taspri__posix-noaltstack.ads \

cross/gcc-armhf/0035-loongarch-disable-multilib-support.patch

@@ -0,0 +1,32 @@
+From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 7 Aug 2023 15:25:58 +0800
+Subject: [PATCH] loongarch disable multilib support
+
+Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
+---
+ gcc/config/loongarch/t-linux    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 23e1fb979..c2753abb8 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -21,11 +21,6 @@ MULTIOSDIR_lp64f := ../lib64/f32$(call if_multiarch,:loongarch64-linux-gnuf32)
+ MULTIOSDIR_lp64s := ../lib64/sf$(call if_multiarch,:loongarch64-linux-gnusf)
+ 
+ # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
+-ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+-
+-    MULTILIB_OSDIRNAMES = .=$(MULTIOSDIR_$(mlib_default))
+-    MULTILIB_OSDIRNAMES += mabi.lp64d=$(MULTIOSDIR_lp64d)
+-    MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+-    MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+-
+-endif
++    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
+-- 
+2.41.0
+

cross/gcc-armhf/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-armhf/0037-loongarch-disable-multilib-support.patch

@@ -1,61 +0,0 @@
-From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
-From: Jingyun Hua <huajingyun@loongson.cn>
-Date: Mon, 7 Aug 2023 15:25:58 +0800
-Subject: [PATCH] loongarch disable multilib support
-
-Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
----
- gcc/config/loongarch/linux.h    | 10 +---------
- gcc/config/loongarch/t-linux    | 18 +++---------------
- 3 files changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
-index 9059d2441..23eaff0cc 100644
---- a/gcc/config/loongarch/linux.h
-+++ b/gcc/config/loongarch/linux.h
-@@ -22,15 +22,7 @@ along with GCC; see the file COPYING3.  If not see
-  * can work in a multilib environment.  */
- 
- #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
--
--  #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
--    #define ABI_LIBDIR "lib64"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
--    #define ABI_LIBDIR "lib64/f32"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64S
--    #define ABI_LIBDIR "lib64/sf"
--  #endif
--
-+    #define ABI_LIBDIR "lib"
- #endif
- 
- #ifndef ABI_LIBDIR
-diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
-index e40da1792..f72c6e878 100644
---- a/gcc/config/loongarch/t-linux
-+++ b/gcc/config/loongarch/t-linux
-@@ -36,18 +36,6 @@ else
- endif
- 
- # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
--ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
--
--    MULTILIB_OSDIRNAMES = \
--      mabi.lp64d=../lib64$\
--      $(call if_multiarch,:loongarch64-linux-gnu)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64f=../lib64/f32$\
--      $(call if_multiarch,:loongarch64-linux-gnuf32)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64s=../lib64/sf$\
--      $(call if_multiarch,:loongarch64-linux-gnusf)
--
--endif
-+    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
--- 
-2.41.0
-

cross/gcc-armhf/APKBUILD

@@ -24,7 +24,7 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-armhf
-pkgver=13.2.1_git20240309
+pkgver=14.2.0
 # i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armhf
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for armhf"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -171,7 +171,7 @@ esac
 # currently on x86, x86_64 and ia64
 _libquadmath=$LANG_FORTRAN
 case "$CTARGET_ARCH" in
-x86 | x86_64 | ppc64le)	_libquadmath=$LANG_FORTRAN ;;
+x86 | x86_64)	_libquadmath=$LANG_FORTRAN ;;
 *)		_libquadmath=false ;;
 esac
 
@@ -241,7 +241,8 @@ makedepends="$makedepends_build $makedepends_host"
 #
 # PLEASE submit all patches to gcc to https://gitlab.alpinelinux.org/kaniini/alpine-gcc-patches,
 # so that they can be properly tracked and easily rebased if needed.
-source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+#source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkgbase:-$pkgver}.tar.xz
 	0001-posix_memalign.patch
 	0002-gcc-poison-system-directories.patch
 	0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -276,8 +277,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-	0037-loongarch-disable-multilib-support.patch
+	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -285,7 +286,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 #     - CVE-2023-4039
 
 # we build out-of-tree
-_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+#_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+_gccdir="$srcdir"/gcc-${_pkgbase:-$pkgver}
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 _gcclibexec="/usr/libexec/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 
@@ -364,7 +366,14 @@ build() {
 	$_libgomp	|| _bootstrap_configure="$_bootstrap_configure --disable-libgomp"
 	$_libatomic	|| _bootstrap_configure="$_bootstrap_configure --disable-libatomic"
 	$_libitm	|| _bootstrap_configure="$_bootstrap_configure --disable-libitm"
-	$_libquadmath	|| _arch_configure="$_arch_configure --disable-libquadmath"
+	if ! $_libquadmath; then
+		_arch_configure="$_arch_configure --disable-libquadmath"
+		# ppc64le needs both --disable-libquadmath{,-support}
+		# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116007
+		[ "$CARCH" = "ppc64le" ] &&
+			_arch_configure="$_arch_configure
+				--disable-libquadmath-support"
+	fi
 
 	msg "Building the following:"
 	echo ""
@@ -793,9 +802,9 @@ gdb() {
 }
 
 sha512sums="
-2d1e0374ebdee526f0549319fc9c364968c52a0d4aaa16759f00453cb083fe58d8f463c47d97f3bb74a0a92e251989eb75a50ee5800b4569978c72d25446b44e  gcc-13-20240309.tar.xz
+932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396  gcc-14.2.0.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
-163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
+1d102a7b17683909dde4d8591dd889149299e77a2b2003cdc0635dc816666be940e41ae534b469485391a9bed183cd5cd337f130e4e1ecb62cb9ad86c4a081db  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
 17a2993027d3ddf8595952ebcae425695ddc7b1cf73b384d2e55fddecb9cbf3f6482860a502ff69b14075e12badf27300fd3039f3a9005e851fd8d121d258c2b  0004-Turn-on-D_FORTIFY_SOURCE-2-by-default-for-C-C-ObjC-O.patch
 444550e55491ff89fe8cbbb4b73d017c9c147cdce1ad5c0561fe7d6ab3834515a814c7676c408cfeec18e1aaace27b3c26a2ffe4a75042285df5124976c38672  0005-On-linux-targets-pass-as-needed-by-default-to-the-li.patch
@@ -806,7 +815,7 @@ sha512sums="
 da9eaf2f0ddbec5ee14dc26053936587e6c76fbf16846db804a18cf4d318579426ebcc566aed02daf8e34f60c08b61f5d3959305886dca9bbcdc84db057258d9  0010-Don-t-declare-asprintf-if-defined-as-a-macro.patch
 35b9aafe7eee8138cb7aad7164a8f77c15ccdce26843cee78b5871ef91d76cad22ed0871b20f51c4b89b71afd9cfe4ba4227086e158c466558513708fe7d2a1a  0011-libiberty-copy-PIC-objects-during-build-process.patch
 9d43f844fad0ac6e1c35a2b6f461f9278ae09e468f2c9ae8adc43accbe6934994aa10d3a433644d1393a4a76e3caed69e3191db7f3c0c24b4e7a0a0a0cbac3f1  0012-libgcc_s.patch
-b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e45334290dbe467a4e891ed34a6522e0c72f746def22e8663  0013-nopie.patch
+91dde3079c1400c124ab5604597f5857185d075809649603aa3641a4581b34029bfcbd4281a5bd925d1c5e6e3b1f5f3322efda34345c6930652d685a6c9525f4  0013-nopie.patch
 0b50ad15115192699efa9fda3d4fb1c2fa95da06d7880ba34615b40c19a8256e1fe364da39f5c70dc22fbccf21db2de5900932afef68948722eeb25e435262f8  0014-ada-fix-shared-linking.patch
 00097c7106625ccf02149a757366f434c48f2abe824bb8b4bf067d29308889cb6039a5e5b2d3bd2683617693b47707d549252c56eea6bc3cdc2450a8d14f46a7  0015-build-fix-CXXFLAGS_FOR_BUILD-passing.patch
 7f0bc42b93a389b614054e700b851abfbc53db391aa10cbdf6990d41396b293af78980bb39f1cf0967184d3fbf3d46ac7c7f096717b8f193ea34cbf7f37d7e91  0016-add-fortify-headers-paths.patch
@@ -816,10 +825,10 @@ b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e
 a9567947471c3ba8a547a79c55e183974554bf823d9a97a165c966d7b3caad8789980e096e3b78452ece5de062bd9bb006af464bbf0c5a35b689eac3ee21e5c5  0020-s390x-disable-multilib-support.patch
 f382eb5f7c2c60c5a23fac587c9629a3059d7be0898e97a1feaf9b9cbe1ef4693cc1177eb29333e8b7944fa17487478e73958be45d5782ccb9ef501961fb9a96  0021-ppc64-le-disable-multilib-support.patch
 44ab86feb8e41e7c2b2e27accdf46194c9b80ee6a39543303dc04824f669d9fad182aabd40c9c7f6c265cf9bb71be830c257be115dc9d701d54eca3aa9ef174e  0022-x86_64-disable-multilib-support.patch
-e0763083c31485e8ac0b3724376a28af01bb6f50e1a054780b61886e4e3de2a35d127e6e353eb8d8729964ada9b5751bf05bdd51df539667008216db38f228a3  0023-riscv-disable-multilib-support.patch
+abf845792433a21fed5dd06167b9f6cf5e8f8026a409acce93824e466c5148e192bf5f404a271931fe4b65283499329bf67bb01019f2f3e02501f20619404e6c  0023-riscv-disable-multilib-support.patch
 ab88a2f63e3545bbc36537aa9a86f2c6c35e41bbf702d6e13743a405cdac4f901eed5737189b780da96647fea9f5d863fdc76373f25a00064106dcb5514d6d87  0024-always-build-libgcc_eh.a.patch
 8fdbe0c8bf4ca60f458a33e59027de03d15ac91933fe46d8ca62119346d20b9bc2447c0bf22bceb63d0cf8613ab61512d9197f4e6c2224af473b63ef9f254295  0025-ada-libgnarl-compatibility-for-musl.patch
-30369bea84020c32d514196ba3adb3d09d2d0359af5550bd3f9719aa357e44b2f695623c1d2a99416e120dc86896c196c5dd4f638183dced4799604137385367  0026-ada-musl-support-fixes.patch
+5fd23a506b55c88d4f000e01c539eb25d6da2516949c9d7a1c9ee20f4c6b627e4788541284d9c14c33bafa7cb43ce2e0469dd91006152f00e30815107150320f  0026-ada-musl-support-fixes.patch
 3f9a406d7d2ce34951215ffbcadb49a45e55ad5c24ab9097c0e5e92383e43b876872ccd2a7e7def2833ab204975ee5733f8bcf90934db9fa9c4f6f56c62081f6  0027-configure-Add-enable-autolink-libatomic-use-in-LINK_.patch
 720a4001f9a1fa4122e456077ecff8d3eb8af7c83d0a81f9da6a6cca05b23664206a82a349e34482c48bfe40e99aa5f21567613d0913f6a24f282bc84a994496  0028-configure-fix-detection-of-atomic-builtins-in-libato.patch
 2044c23b23726965c0a6fd39f616cc464badd650947cb40495eeabd906a3af629878c1d28b403b8eb46b30a1a0ba39083023290d62f0c99ccf070063226e3f8f  0029-libstdc-do-not-throw-exceptions-for-non-C-locales-on.patch
@@ -828,6 +837,6 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-d834f5f95f4ebe70ec0af0748c8632c99a4f57b69dc14db1a38becdfcb03406b32febf39f772f37bd145538147099fa7433edce845e14ee77cd8f38fd9774fc1  0037-loongarch-disable-multilib-support.patch
+65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-armhf/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-armv7/0002-gcc-poison-system-directories.patch

@@ -150,13 +150,13 @@ diff --git a/gcc/gcc.cc b/gcc/gcc.cc
 index 16bb07f2cdc..33b56e721d2 100644
 --- a/gcc/gcc.cc
 +++ b/gcc/gcc.cc
-@@ -1146,6 +1146,8 @@ proper position among the other output files.  */
-    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+@@ -1177,6 +1187,8 @@ proper position among the other output files.  */
+    "-z now " \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
 +    %{Wno-poison-system-directories:--no-poison-system-directories} \
 +    %{Werror=poison-system-directories:--error-poison-system-directories} \
-     %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
+     %{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
 diff --git a/gcc/incpath.cc b/gcc/incpath.cc

cross/gcc-armv7/0013-nopie.patch

@@ -9,23 +9,22 @@ Subject: [PATCH 13/35] nopie
  2 files changed, 40 insertions(+)
 
 diff --git a/gcc/configure b/gcc/configure
-index 8c46369f73f..e59cbee1767 100755
+index 23da7d55d..f38732bb2 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -32268,6 +32268,33 @@ fi
+@@ -34534,6 +34534,29 @@ rm -f core conftest.err conftest.$ac_objext \
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie" >&5
  $as_echo "$gcc_cv_no_pie" >&6; }
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
++# Check if -nopie works.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
 +$as_echo_n "checking for -nopie option... " >&6; }
-+if test "${gcc_cv_nopie+set}" = set; then :
++if ${gcc_cv_nopie+:} false; then :
 +  $as_echo_n "(cached) " >&6
 +else
 +  saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++   LDFLAGS="$LDFLAGS -nopie"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 +/* end confdefs.h.  */
 +int main(void) {return 0;}
 +_ACEOF
@@ -36,40 +35,51 @@ index 8c46369f73f..e59cbee1767 100755
 +fi
 +rm -f core conftest.err conftest.$ac_objext \
 +    conftest$ac_exeext conftest.$ac_ext
-+     LDFLAGS="$saved_LDFLAGS"
++   LDFLAGS="$saved_LDFLAGS"
 +fi
 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_nopie" >&5
 +$as_echo "$gcc_cv_nopie" >&6; }
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
+ 
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -34551,6 +34574,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
  fi
- 
- 
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 5504bf6eb01..57268319de1 100644
+index d7cf0b92c..db2e2c802 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7552,6 +7552,19 @@ AC_CACHE_CHECK([for -no-pie option],
+@@ -7781,6 +7781,15 @@ AC_CACHE_CHECK([for -no-pie option],
+      [gcc_cv_no_pie=yes],
+      [gcc_cv_no_pie=no])
     LDFLAGS="$saved_LDFLAGS"])
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  AC_CACHE_CHECK([for -nopie option],
-+    [gcc_cv_nopie],
-+    [saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     AC_LINK_IFELSE([int main(void) {return 0;}],
-+       [gcc_cv_nopie=yes],
-+       [gcc_cv_nopie=no])
-+     LDFLAGS="$saved_LDFLAGS"])
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
- fi
- AC_SUBST([NO_PIE_FLAG])
++# Check if -nopie works.
++AC_CACHE_CHECK([for -nopie option],
++  [gcc_cv_nopie],
++  [saved_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -nopie"
++   AC_LINK_IFELSE([AC_LANG_SOURCE([int main(void) {return 0;}])],
++     [gcc_cv_nopie=yes],
++     [gcc_cv_nopie=no])
++   LDFLAGS="$saved_LDFLAGS"])
  
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -7798,6 +7807,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
+ fi
 -- 
 2.41.0
 

cross/gcc-armv7/0023-riscv-disable-multilib-support.patch

@@ -46,10 +46,10 @@ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index f8c2c351e5a..8d9881eadeb 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
-@@ -61,11 +61,3 @@ along with GCC; see the file COPYING3.  If not see
-     %{static:-static}}"
- 
- #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+@@ -60,11 +60,3 @@ along with GCC; see the file COPYING3.  If not see
+ 	%{rdynamic:-export-dynamic} \
+ 	-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
 -
 -#define STARTFILE_PREFIX_SPEC 			\
 -   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\

cross/gcc-armv7/0026-ada-musl-support-fixes.patch

@@ -41,6 +41,15 @@ index 96306f8cc9a..090b6770ae5 100644
    LIBGNAT_TARGET_PAIRS = \
    a-intnam.ads<libgnarl/a-intnam__linux.ads \
    s-inmaop.adb<libgnarl/s-inmaop__posix.adb \
+@@ -2311,7 +2311,7 @@ ifeq ($(strip $(filter-out aarch64% linux%,$(target_cpu) $(target_os))),)
+   s-intman.adb<libgnarl/s-intman__posix.adb \
+   s-linux.ads<libgnarl/s-linux.ads \
+   $(TRASYM_DWARF_UNIX_PAIRS) \
+-  s-tsmona.adb<libgnat/s-tsmona__linux.adb \
++  s-tsmona.adb<libgnat/s-tsmona.adb \
+   s-mudido.adb<libgnarl/s-mudido__affinity.adb \
+   s-osinte.ads<libgnarl/s-osinte__linux.ads \
+   s-osinte.adb<libgnarl/s-osinte__posix.adb \
 @@ -2420,7 +2420,7 @@ ifeq ($(strip $(filter-out %ia64 linux%,$(target_cpu) $(target_os))),)
    s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \
    s-taspri.ads<libgnarl/s-taspri__posix-noaltstack.ads \

cross/gcc-armv7/0035-loongarch-disable-multilib-support.patch

@@ -0,0 +1,32 @@
+From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 7 Aug 2023 15:25:58 +0800
+Subject: [PATCH] loongarch disable multilib support
+
+Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
+---
+ gcc/config/loongarch/t-linux    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 23e1fb979..c2753abb8 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -21,11 +21,6 @@ MULTIOSDIR_lp64f := ../lib64/f32$(call if_multiarch,:loongarch64-linux-gnuf32)
+ MULTIOSDIR_lp64s := ../lib64/sf$(call if_multiarch,:loongarch64-linux-gnusf)
+ 
+ # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
+-ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+-
+-    MULTILIB_OSDIRNAMES = .=$(MULTIOSDIR_$(mlib_default))
+-    MULTILIB_OSDIRNAMES += mabi.lp64d=$(MULTIOSDIR_lp64d)
+-    MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+-    MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+-
+-endif
++    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
+-- 
+2.41.0
+

cross/gcc-armv7/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-armv7/0037-loongarch-disable-multilib-support.patch

@@ -1,61 +0,0 @@
-From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
-From: Jingyun Hua <huajingyun@loongson.cn>
-Date: Mon, 7 Aug 2023 15:25:58 +0800
-Subject: [PATCH] loongarch disable multilib support
-
-Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
----
- gcc/config/loongarch/linux.h    | 10 +---------
- gcc/config/loongarch/t-linux    | 18 +++---------------
- 3 files changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
-index 9059d2441..23eaff0cc 100644
---- a/gcc/config/loongarch/linux.h
-+++ b/gcc/config/loongarch/linux.h
-@@ -22,15 +22,7 @@ along with GCC; see the file COPYING3.  If not see
-  * can work in a multilib environment.  */
- 
- #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
--
--  #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
--    #define ABI_LIBDIR "lib64"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
--    #define ABI_LIBDIR "lib64/f32"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64S
--    #define ABI_LIBDIR "lib64/sf"
--  #endif
--
-+    #define ABI_LIBDIR "lib"
- #endif
- 
- #ifndef ABI_LIBDIR
-diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
-index e40da1792..f72c6e878 100644
---- a/gcc/config/loongarch/t-linux
-+++ b/gcc/config/loongarch/t-linux
-@@ -36,18 +36,6 @@ else
- endif
- 
- # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
--ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
--
--    MULTILIB_OSDIRNAMES = \
--      mabi.lp64d=../lib64$\
--      $(call if_multiarch,:loongarch64-linux-gnu)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64f=../lib64/f32$\
--      $(call if_multiarch,:loongarch64-linux-gnuf32)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64s=../lib64/sf$\
--      $(call if_multiarch,:loongarch64-linux-gnusf)
--
--endif
-+    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
--- 
-2.41.0
-

cross/gcc-armv7/APKBUILD

@@ -24,7 +24,7 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-armv7
-pkgver=13.2.1_git20240309
+pkgver=14.2.0
 # i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armv7
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for armv7"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -171,7 +171,7 @@ esac
 # currently on x86, x86_64 and ia64
 _libquadmath=$LANG_FORTRAN
 case "$CTARGET_ARCH" in
-x86 | x86_64 | ppc64le)	_libquadmath=$LANG_FORTRAN ;;
+x86 | x86_64)	_libquadmath=$LANG_FORTRAN ;;
 *)		_libquadmath=false ;;
 esac
 
@@ -241,7 +241,8 @@ makedepends="$makedepends_build $makedepends_host"
 #
 # PLEASE submit all patches to gcc to https://gitlab.alpinelinux.org/kaniini/alpine-gcc-patches,
 # so that they can be properly tracked and easily rebased if needed.
-source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+#source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkgbase:-$pkgver}.tar.xz
 	0001-posix_memalign.patch
 	0002-gcc-poison-system-directories.patch
 	0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -276,8 +277,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-	0037-loongarch-disable-multilib-support.patch
+	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -285,7 +286,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 #     - CVE-2023-4039
 
 # we build out-of-tree
-_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+#_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+_gccdir="$srcdir"/gcc-${_pkgbase:-$pkgver}
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 _gcclibexec="/usr/libexec/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 
@@ -364,7 +366,14 @@ build() {
 	$_libgomp	|| _bootstrap_configure="$_bootstrap_configure --disable-libgomp"
 	$_libatomic	|| _bootstrap_configure="$_bootstrap_configure --disable-libatomic"
 	$_libitm	|| _bootstrap_configure="$_bootstrap_configure --disable-libitm"
-	$_libquadmath	|| _arch_configure="$_arch_configure --disable-libquadmath"
+	if ! $_libquadmath; then
+		_arch_configure="$_arch_configure --disable-libquadmath"
+		# ppc64le needs both --disable-libquadmath{,-support}
+		# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116007
+		[ "$CARCH" = "ppc64le" ] &&
+			_arch_configure="$_arch_configure
+				--disable-libquadmath-support"
+	fi
 
 	msg "Building the following:"
 	echo ""
@@ -793,9 +802,9 @@ gdb() {
 }
 
 sha512sums="
-2d1e0374ebdee526f0549319fc9c364968c52a0d4aaa16759f00453cb083fe58d8f463c47d97f3bb74a0a92e251989eb75a50ee5800b4569978c72d25446b44e  gcc-13-20240309.tar.xz
+932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396  gcc-14.2.0.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
-163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
+1d102a7b17683909dde4d8591dd889149299e77a2b2003cdc0635dc816666be940e41ae534b469485391a9bed183cd5cd337f130e4e1ecb62cb9ad86c4a081db  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
 17a2993027d3ddf8595952ebcae425695ddc7b1cf73b384d2e55fddecb9cbf3f6482860a502ff69b14075e12badf27300fd3039f3a9005e851fd8d121d258c2b  0004-Turn-on-D_FORTIFY_SOURCE-2-by-default-for-C-C-ObjC-O.patch
 444550e55491ff89fe8cbbb4b73d017c9c147cdce1ad5c0561fe7d6ab3834515a814c7676c408cfeec18e1aaace27b3c26a2ffe4a75042285df5124976c38672  0005-On-linux-targets-pass-as-needed-by-default-to-the-li.patch
@@ -806,7 +815,7 @@ sha512sums="
 da9eaf2f0ddbec5ee14dc26053936587e6c76fbf16846db804a18cf4d318579426ebcc566aed02daf8e34f60c08b61f5d3959305886dca9bbcdc84db057258d9  0010-Don-t-declare-asprintf-if-defined-as-a-macro.patch
 35b9aafe7eee8138cb7aad7164a8f77c15ccdce26843cee78b5871ef91d76cad22ed0871b20f51c4b89b71afd9cfe4ba4227086e158c466558513708fe7d2a1a  0011-libiberty-copy-PIC-objects-during-build-process.patch
 9d43f844fad0ac6e1c35a2b6f461f9278ae09e468f2c9ae8adc43accbe6934994aa10d3a433644d1393a4a76e3caed69e3191db7f3c0c24b4e7a0a0a0cbac3f1  0012-libgcc_s.patch
-b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e45334290dbe467a4e891ed34a6522e0c72f746def22e8663  0013-nopie.patch
+91dde3079c1400c124ab5604597f5857185d075809649603aa3641a4581b34029bfcbd4281a5bd925d1c5e6e3b1f5f3322efda34345c6930652d685a6c9525f4  0013-nopie.patch
 0b50ad15115192699efa9fda3d4fb1c2fa95da06d7880ba34615b40c19a8256e1fe364da39f5c70dc22fbccf21db2de5900932afef68948722eeb25e435262f8  0014-ada-fix-shared-linking.patch
 00097c7106625ccf02149a757366f434c48f2abe824bb8b4bf067d29308889cb6039a5e5b2d3bd2683617693b47707d549252c56eea6bc3cdc2450a8d14f46a7  0015-build-fix-CXXFLAGS_FOR_BUILD-passing.patch
 7f0bc42b93a389b614054e700b851abfbc53db391aa10cbdf6990d41396b293af78980bb39f1cf0967184d3fbf3d46ac7c7f096717b8f193ea34cbf7f37d7e91  0016-add-fortify-headers-paths.patch
@@ -816,10 +825,10 @@ b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e
 a9567947471c3ba8a547a79c55e183974554bf823d9a97a165c966d7b3caad8789980e096e3b78452ece5de062bd9bb006af464bbf0c5a35b689eac3ee21e5c5  0020-s390x-disable-multilib-support.patch
 f382eb5f7c2c60c5a23fac587c9629a3059d7be0898e97a1feaf9b9cbe1ef4693cc1177eb29333e8b7944fa17487478e73958be45d5782ccb9ef501961fb9a96  0021-ppc64-le-disable-multilib-support.patch
 44ab86feb8e41e7c2b2e27accdf46194c9b80ee6a39543303dc04824f669d9fad182aabd40c9c7f6c265cf9bb71be830c257be115dc9d701d54eca3aa9ef174e  0022-x86_64-disable-multilib-support.patch
-e0763083c31485e8ac0b3724376a28af01bb6f50e1a054780b61886e4e3de2a35d127e6e353eb8d8729964ada9b5751bf05bdd51df539667008216db38f228a3  0023-riscv-disable-multilib-support.patch
+abf845792433a21fed5dd06167b9f6cf5e8f8026a409acce93824e466c5148e192bf5f404a271931fe4b65283499329bf67bb01019f2f3e02501f20619404e6c  0023-riscv-disable-multilib-support.patch
 ab88a2f63e3545bbc36537aa9a86f2c6c35e41bbf702d6e13743a405cdac4f901eed5737189b780da96647fea9f5d863fdc76373f25a00064106dcb5514d6d87  0024-always-build-libgcc_eh.a.patch
 8fdbe0c8bf4ca60f458a33e59027de03d15ac91933fe46d8ca62119346d20b9bc2447c0bf22bceb63d0cf8613ab61512d9197f4e6c2224af473b63ef9f254295  0025-ada-libgnarl-compatibility-for-musl.patch
-30369bea84020c32d514196ba3adb3d09d2d0359af5550bd3f9719aa357e44b2f695623c1d2a99416e120dc86896c196c5dd4f638183dced4799604137385367  0026-ada-musl-support-fixes.patch
+5fd23a506b55c88d4f000e01c539eb25d6da2516949c9d7a1c9ee20f4c6b627e4788541284d9c14c33bafa7cb43ce2e0469dd91006152f00e30815107150320f  0026-ada-musl-support-fixes.patch
 3f9a406d7d2ce34951215ffbcadb49a45e55ad5c24ab9097c0e5e92383e43b876872ccd2a7e7def2833ab204975ee5733f8bcf90934db9fa9c4f6f56c62081f6  0027-configure-Add-enable-autolink-libatomic-use-in-LINK_.patch
 720a4001f9a1fa4122e456077ecff8d3eb8af7c83d0a81f9da6a6cca05b23664206a82a349e34482c48bfe40e99aa5f21567613d0913f6a24f282bc84a994496  0028-configure-fix-detection-of-atomic-builtins-in-libato.patch
 2044c23b23726965c0a6fd39f616cc464badd650947cb40495eeabd906a3af629878c1d28b403b8eb46b30a1a0ba39083023290d62f0c99ccf070063226e3f8f  0029-libstdc-do-not-throw-exceptions-for-non-C-locales-on.patch
@@ -828,6 +837,6 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-d834f5f95f4ebe70ec0af0748c8632c99a4f57b69dc14db1a38becdfcb03406b32febf39f772f37bd145538147099fa7433edce845e14ee77cd8f38fd9774fc1  0037-loongarch-disable-multilib-support.patch
+65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-armv7/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-riscv64/0002-gcc-poison-system-directories.patch

@@ -150,13 +150,13 @@ diff --git a/gcc/gcc.cc b/gcc/gcc.cc
 index 16bb07f2cdc..33b56e721d2 100644
 --- a/gcc/gcc.cc
 +++ b/gcc/gcc.cc
-@@ -1146,6 +1146,8 @@ proper position among the other output files.  */
-    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+@@ -1177,6 +1187,8 @@ proper position among the other output files.  */
+    "-z now " \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
 +    %{Wno-poison-system-directories:--no-poison-system-directories} \
 +    %{Werror=poison-system-directories:--error-poison-system-directories} \
-     %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
+     %{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
 diff --git a/gcc/incpath.cc b/gcc/incpath.cc

cross/gcc-riscv64/0013-nopie.patch

@@ -9,23 +9,22 @@ Subject: [PATCH 13/35] nopie
  2 files changed, 40 insertions(+)
 
 diff --git a/gcc/configure b/gcc/configure
-index 8c46369f73f..e59cbee1767 100755
+index 23da7d55d..f38732bb2 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -32268,6 +32268,33 @@ fi
+@@ -34534,6 +34534,29 @@ rm -f core conftest.err conftest.$ac_objext \
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie" >&5
  $as_echo "$gcc_cv_no_pie" >&6; }
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
++# Check if -nopie works.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
 +$as_echo_n "checking for -nopie option... " >&6; }
-+if test "${gcc_cv_nopie+set}" = set; then :
++if ${gcc_cv_nopie+:} false; then :
 +  $as_echo_n "(cached) " >&6
 +else
 +  saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++   LDFLAGS="$LDFLAGS -nopie"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 +/* end confdefs.h.  */
 +int main(void) {return 0;}
 +_ACEOF
@@ -36,40 +35,51 @@ index 8c46369f73f..e59cbee1767 100755
 +fi
 +rm -f core conftest.err conftest.$ac_objext \
 +    conftest$ac_exeext conftest.$ac_ext
-+     LDFLAGS="$saved_LDFLAGS"
++   LDFLAGS="$saved_LDFLAGS"
 +fi
 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_nopie" >&5
 +$as_echo "$gcc_cv_nopie" >&6; }
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
+ 
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -34551,6 +34574,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
  fi
- 
- 
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 5504bf6eb01..57268319de1 100644
+index d7cf0b92c..db2e2c802 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7552,6 +7552,19 @@ AC_CACHE_CHECK([for -no-pie option],
+@@ -7781,6 +7781,15 @@ AC_CACHE_CHECK([for -no-pie option],
+      [gcc_cv_no_pie=yes],
+      [gcc_cv_no_pie=no])
     LDFLAGS="$saved_LDFLAGS"])
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  AC_CACHE_CHECK([for -nopie option],
-+    [gcc_cv_nopie],
-+    [saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     AC_LINK_IFELSE([int main(void) {return 0;}],
-+       [gcc_cv_nopie=yes],
-+       [gcc_cv_nopie=no])
-+     LDFLAGS="$saved_LDFLAGS"])
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
- fi
- AC_SUBST([NO_PIE_FLAG])
++# Check if -nopie works.
++AC_CACHE_CHECK([for -nopie option],
++  [gcc_cv_nopie],
++  [saved_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -nopie"
++   AC_LINK_IFELSE([AC_LANG_SOURCE([int main(void) {return 0;}])],
++     [gcc_cv_nopie=yes],
++     [gcc_cv_nopie=no])
++   LDFLAGS="$saved_LDFLAGS"])
  
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -7798,6 +7807,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
+ fi
 -- 
 2.41.0
 

cross/gcc-riscv64/0023-riscv-disable-multilib-support.patch

@@ -46,10 +46,10 @@ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index f8c2c351e5a..8d9881eadeb 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
-@@ -61,11 +61,3 @@ along with GCC; see the file COPYING3.  If not see
-     %{static:-static}}"
- 
- #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+@@ -60,11 +60,3 @@ along with GCC; see the file COPYING3.  If not see
+ 	%{rdynamic:-export-dynamic} \
+ 	-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
 -
 -#define STARTFILE_PREFIX_SPEC 			\
 -   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\

cross/gcc-riscv64/0026-ada-musl-support-fixes.patch

@@ -41,6 +41,15 @@ index 96306f8cc9a..090b6770ae5 100644
    LIBGNAT_TARGET_PAIRS = \
    a-intnam.ads<libgnarl/a-intnam__linux.ads \
    s-inmaop.adb<libgnarl/s-inmaop__posix.adb \
+@@ -2311,7 +2311,7 @@ ifeq ($(strip $(filter-out aarch64% linux%,$(target_cpu) $(target_os))),)
+   s-intman.adb<libgnarl/s-intman__posix.adb \
+   s-linux.ads<libgnarl/s-linux.ads \
+   $(TRASYM_DWARF_UNIX_PAIRS) \
+-  s-tsmona.adb<libgnat/s-tsmona__linux.adb \
++  s-tsmona.adb<libgnat/s-tsmona.adb \
+   s-mudido.adb<libgnarl/s-mudido__affinity.adb \
+   s-osinte.ads<libgnarl/s-osinte__linux.ads \
+   s-osinte.adb<libgnarl/s-osinte__posix.adb \
 @@ -2420,7 +2420,7 @@ ifeq ($(strip $(filter-out %ia64 linux%,$(target_cpu) $(target_os))),)
    s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \
    s-taspri.ads<libgnarl/s-taspri__posix-noaltstack.ads \

cross/gcc-riscv64/0035-loongarch-disable-multilib-support.patch

@@ -0,0 +1,32 @@
+From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 7 Aug 2023 15:25:58 +0800
+Subject: [PATCH] loongarch disable multilib support
+
+Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
+---
+ gcc/config/loongarch/t-linux    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 23e1fb979..c2753abb8 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -21,11 +21,6 @@ MULTIOSDIR_lp64f := ../lib64/f32$(call if_multiarch,:loongarch64-linux-gnuf32)
+ MULTIOSDIR_lp64s := ../lib64/sf$(call if_multiarch,:loongarch64-linux-gnusf)
+ 
+ # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
+-ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+-
+-    MULTILIB_OSDIRNAMES = .=$(MULTIOSDIR_$(mlib_default))
+-    MULTILIB_OSDIRNAMES += mabi.lp64d=$(MULTIOSDIR_lp64d)
+-    MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+-    MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+-
+-endif
++    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
+-- 
+2.41.0
+

cross/gcc-riscv64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-riscv64/0037-loongarch-disable-multilib-support.patch

@@ -1,61 +0,0 @@
-From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
-From: Jingyun Hua <huajingyun@loongson.cn>
-Date: Mon, 7 Aug 2023 15:25:58 +0800
-Subject: [PATCH] loongarch disable multilib support
-
-Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
----
- gcc/config/loongarch/linux.h    | 10 +---------
- gcc/config/loongarch/t-linux    | 18 +++---------------
- 3 files changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
-index 9059d2441..23eaff0cc 100644
---- a/gcc/config/loongarch/linux.h
-+++ b/gcc/config/loongarch/linux.h
-@@ -22,15 +22,7 @@ along with GCC; see the file COPYING3.  If not see
-  * can work in a multilib environment.  */
- 
- #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
--
--  #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
--    #define ABI_LIBDIR "lib64"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
--    #define ABI_LIBDIR "lib64/f32"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64S
--    #define ABI_LIBDIR "lib64/sf"
--  #endif
--
-+    #define ABI_LIBDIR "lib"
- #endif
- 
- #ifndef ABI_LIBDIR
-diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
-index e40da1792..f72c6e878 100644
---- a/gcc/config/loongarch/t-linux
-+++ b/gcc/config/loongarch/t-linux
-@@ -36,18 +36,6 @@ else
- endif
- 
- # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
--ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
--
--    MULTILIB_OSDIRNAMES = \
--      mabi.lp64d=../lib64$\
--      $(call if_multiarch,:loongarch64-linux-gnu)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64f=../lib64/f32$\
--      $(call if_multiarch,:loongarch64-linux-gnuf32)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64s=../lib64/sf$\
--      $(call if_multiarch,:loongarch64-linux-gnusf)
--
--endif
-+    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
--- 
-2.41.0
-

cross/gcc-riscv64/APKBUILD

@@ -24,7 +24,7 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-riscv64
-pkgver=13.2.1_git20240309
+pkgver=14.2.0
 # i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-riscv64
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for riscv64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -171,7 +171,7 @@ esac
 # currently on x86, x86_64 and ia64
 _libquadmath=$LANG_FORTRAN
 case "$CTARGET_ARCH" in
-x86 | x86_64 | ppc64le)	_libquadmath=$LANG_FORTRAN ;;
+x86 | x86_64)	_libquadmath=$LANG_FORTRAN ;;
 *)		_libquadmath=false ;;
 esac
 
@@ -241,7 +241,8 @@ makedepends="$makedepends_build $makedepends_host"
 #
 # PLEASE submit all patches to gcc to https://gitlab.alpinelinux.org/kaniini/alpine-gcc-patches,
 # so that they can be properly tracked and easily rebased if needed.
-source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+#source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkgbase:-$pkgver}.tar.xz
 	0001-posix_memalign.patch
 	0002-gcc-poison-system-directories.patch
 	0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -276,8 +277,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-	0037-loongarch-disable-multilib-support.patch
+	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -285,7 +286,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 #     - CVE-2023-4039
 
 # we build out-of-tree
-_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+#_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+_gccdir="$srcdir"/gcc-${_pkgbase:-$pkgver}
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 _gcclibexec="/usr/libexec/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 
@@ -364,7 +366,14 @@ build() {
 	$_libgomp	|| _bootstrap_configure="$_bootstrap_configure --disable-libgomp"
 	$_libatomic	|| _bootstrap_configure="$_bootstrap_configure --disable-libatomic"
 	$_libitm	|| _bootstrap_configure="$_bootstrap_configure --disable-libitm"
-	$_libquadmath	|| _arch_configure="$_arch_configure --disable-libquadmath"
+	if ! $_libquadmath; then
+		_arch_configure="$_arch_configure --disable-libquadmath"
+		# ppc64le needs both --disable-libquadmath{,-support}
+		# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116007
+		[ "$CARCH" = "ppc64le" ] &&
+			_arch_configure="$_arch_configure
+				--disable-libquadmath-support"
+	fi
 
 	msg "Building the following:"
 	echo ""
@@ -793,9 +802,9 @@ gdb() {
 }
 
 sha512sums="
-2d1e0374ebdee526f0549319fc9c364968c52a0d4aaa16759f00453cb083fe58d8f463c47d97f3bb74a0a92e251989eb75a50ee5800b4569978c72d25446b44e  gcc-13-20240309.tar.xz
+932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396  gcc-14.2.0.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
-163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
+1d102a7b17683909dde4d8591dd889149299e77a2b2003cdc0635dc816666be940e41ae534b469485391a9bed183cd5cd337f130e4e1ecb62cb9ad86c4a081db  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
 17a2993027d3ddf8595952ebcae425695ddc7b1cf73b384d2e55fddecb9cbf3f6482860a502ff69b14075e12badf27300fd3039f3a9005e851fd8d121d258c2b  0004-Turn-on-D_FORTIFY_SOURCE-2-by-default-for-C-C-ObjC-O.patch
 444550e55491ff89fe8cbbb4b73d017c9c147cdce1ad5c0561fe7d6ab3834515a814c7676c408cfeec18e1aaace27b3c26a2ffe4a75042285df5124976c38672  0005-On-linux-targets-pass-as-needed-by-default-to-the-li.patch
@@ -806,7 +815,7 @@ sha512sums="
 da9eaf2f0ddbec5ee14dc26053936587e6c76fbf16846db804a18cf4d318579426ebcc566aed02daf8e34f60c08b61f5d3959305886dca9bbcdc84db057258d9  0010-Don-t-declare-asprintf-if-defined-as-a-macro.patch
 35b9aafe7eee8138cb7aad7164a8f77c15ccdce26843cee78b5871ef91d76cad22ed0871b20f51c4b89b71afd9cfe4ba4227086e158c466558513708fe7d2a1a  0011-libiberty-copy-PIC-objects-during-build-process.patch
 9d43f844fad0ac6e1c35a2b6f461f9278ae09e468f2c9ae8adc43accbe6934994aa10d3a433644d1393a4a76e3caed69e3191db7f3c0c24b4e7a0a0a0cbac3f1  0012-libgcc_s.patch
-b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e45334290dbe467a4e891ed34a6522e0c72f746def22e8663  0013-nopie.patch
+91dde3079c1400c124ab5604597f5857185d075809649603aa3641a4581b34029bfcbd4281a5bd925d1c5e6e3b1f5f3322efda34345c6930652d685a6c9525f4  0013-nopie.patch
 0b50ad15115192699efa9fda3d4fb1c2fa95da06d7880ba34615b40c19a8256e1fe364da39f5c70dc22fbccf21db2de5900932afef68948722eeb25e435262f8  0014-ada-fix-shared-linking.patch
 00097c7106625ccf02149a757366f434c48f2abe824bb8b4bf067d29308889cb6039a5e5b2d3bd2683617693b47707d549252c56eea6bc3cdc2450a8d14f46a7  0015-build-fix-CXXFLAGS_FOR_BUILD-passing.patch
 7f0bc42b93a389b614054e700b851abfbc53db391aa10cbdf6990d41396b293af78980bb39f1cf0967184d3fbf3d46ac7c7f096717b8f193ea34cbf7f37d7e91  0016-add-fortify-headers-paths.patch
@@ -816,10 +825,10 @@ b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e
 a9567947471c3ba8a547a79c55e183974554bf823d9a97a165c966d7b3caad8789980e096e3b78452ece5de062bd9bb006af464bbf0c5a35b689eac3ee21e5c5  0020-s390x-disable-multilib-support.patch
 f382eb5f7c2c60c5a23fac587c9629a3059d7be0898e97a1feaf9b9cbe1ef4693cc1177eb29333e8b7944fa17487478e73958be45d5782ccb9ef501961fb9a96  0021-ppc64-le-disable-multilib-support.patch
 44ab86feb8e41e7c2b2e27accdf46194c9b80ee6a39543303dc04824f669d9fad182aabd40c9c7f6c265cf9bb71be830c257be115dc9d701d54eca3aa9ef174e  0022-x86_64-disable-multilib-support.patch
-e0763083c31485e8ac0b3724376a28af01bb6f50e1a054780b61886e4e3de2a35d127e6e353eb8d8729964ada9b5751bf05bdd51df539667008216db38f228a3  0023-riscv-disable-multilib-support.patch
+abf845792433a21fed5dd06167b9f6cf5e8f8026a409acce93824e466c5148e192bf5f404a271931fe4b65283499329bf67bb01019f2f3e02501f20619404e6c  0023-riscv-disable-multilib-support.patch
 ab88a2f63e3545bbc36537aa9a86f2c6c35e41bbf702d6e13743a405cdac4f901eed5737189b780da96647fea9f5d863fdc76373f25a00064106dcb5514d6d87  0024-always-build-libgcc_eh.a.patch
 8fdbe0c8bf4ca60f458a33e59027de03d15ac91933fe46d8ca62119346d20b9bc2447c0bf22bceb63d0cf8613ab61512d9197f4e6c2224af473b63ef9f254295  0025-ada-libgnarl-compatibility-for-musl.patch
-30369bea84020c32d514196ba3adb3d09d2d0359af5550bd3f9719aa357e44b2f695623c1d2a99416e120dc86896c196c5dd4f638183dced4799604137385367  0026-ada-musl-support-fixes.patch
+5fd23a506b55c88d4f000e01c539eb25d6da2516949c9d7a1c9ee20f4c6b627e4788541284d9c14c33bafa7cb43ce2e0469dd91006152f00e30815107150320f  0026-ada-musl-support-fixes.patch
 3f9a406d7d2ce34951215ffbcadb49a45e55ad5c24ab9097c0e5e92383e43b876872ccd2a7e7def2833ab204975ee5733f8bcf90934db9fa9c4f6f56c62081f6  0027-configure-Add-enable-autolink-libatomic-use-in-LINK_.patch
 720a4001f9a1fa4122e456077ecff8d3eb8af7c83d0a81f9da6a6cca05b23664206a82a349e34482c48bfe40e99aa5f21567613d0913f6a24f282bc84a994496  0028-configure-fix-detection-of-atomic-builtins-in-libato.patch
 2044c23b23726965c0a6fd39f616cc464badd650947cb40495eeabd906a3af629878c1d28b403b8eb46b30a1a0ba39083023290d62f0c99ccf070063226e3f8f  0029-libstdc-do-not-throw-exceptions-for-non-C-locales-on.patch
@@ -828,6 +837,6 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-d834f5f95f4ebe70ec0af0748c8632c99a4f57b69dc14db1a38becdfcb03406b32febf39f772f37bd145538147099fa7433edce845e14ee77cd8f38fd9774fc1  0037-loongarch-disable-multilib-support.patch
+65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-riscv64/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-x86/0002-gcc-poison-system-directories.patch

@@ -150,13 +150,13 @@ diff --git a/gcc/gcc.cc b/gcc/gcc.cc
 index 16bb07f2cdc..33b56e721d2 100644
 --- a/gcc/gcc.cc
 +++ b/gcc/gcc.cc
-@@ -1146,6 +1146,8 @@ proper position among the other output files.  */
-    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+@@ -1177,6 +1187,8 @@ proper position among the other output files.  */
+    "-z now " \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
 +    %{Wno-poison-system-directories:--no-poison-system-directories} \
 +    %{Werror=poison-system-directories:--error-poison-system-directories} \
-     %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
+     %{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
 diff --git a/gcc/incpath.cc b/gcc/incpath.cc

cross/gcc-x86/0013-nopie.patch

@@ -9,23 +9,22 @@ Subject: [PATCH 13/35] nopie
  2 files changed, 40 insertions(+)
 
 diff --git a/gcc/configure b/gcc/configure
-index 8c46369f73f..e59cbee1767 100755
+index 23da7d55d..f38732bb2 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -32268,6 +32268,33 @@ fi
+@@ -34534,6 +34534,29 @@ rm -f core conftest.err conftest.$ac_objext \
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie" >&5
  $as_echo "$gcc_cv_no_pie" >&6; }
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
++# Check if -nopie works.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
 +$as_echo_n "checking for -nopie option... " >&6; }
-+if test "${gcc_cv_nopie+set}" = set; then :
++if ${gcc_cv_nopie+:} false; then :
 +  $as_echo_n "(cached) " >&6
 +else
 +  saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++   LDFLAGS="$LDFLAGS -nopie"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 +/* end confdefs.h.  */
 +int main(void) {return 0;}
 +_ACEOF
@@ -36,40 +35,51 @@ index 8c46369f73f..e59cbee1767 100755
 +fi
 +rm -f core conftest.err conftest.$ac_objext \
 +    conftest$ac_exeext conftest.$ac_ext
-+     LDFLAGS="$saved_LDFLAGS"
++   LDFLAGS="$saved_LDFLAGS"
 +fi
 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_nopie" >&5
 +$as_echo "$gcc_cv_nopie" >&6; }
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
+ 
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -34551,6 +34574,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
  fi
- 
- 
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 5504bf6eb01..57268319de1 100644
+index d7cf0b92c..db2e2c802 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7552,6 +7552,19 @@ AC_CACHE_CHECK([for -no-pie option],
+@@ -7781,6 +7781,15 @@ AC_CACHE_CHECK([for -no-pie option],
+      [gcc_cv_no_pie=yes],
+      [gcc_cv_no_pie=no])
     LDFLAGS="$saved_LDFLAGS"])
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  AC_CACHE_CHECK([for -nopie option],
-+    [gcc_cv_nopie],
-+    [saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     AC_LINK_IFELSE([int main(void) {return 0;}],
-+       [gcc_cv_nopie=yes],
-+       [gcc_cv_nopie=no])
-+     LDFLAGS="$saved_LDFLAGS"])
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
- fi
- AC_SUBST([NO_PIE_FLAG])
++# Check if -nopie works.
++AC_CACHE_CHECK([for -nopie option],
++  [gcc_cv_nopie],
++  [saved_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -nopie"
++   AC_LINK_IFELSE([AC_LANG_SOURCE([int main(void) {return 0;}])],
++     [gcc_cv_nopie=yes],
++     [gcc_cv_nopie=no])
++   LDFLAGS="$saved_LDFLAGS"])
  
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -7798,6 +7807,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
+ fi
 -- 
 2.41.0
 

cross/gcc-x86/0023-riscv-disable-multilib-support.patch

@@ -46,10 +46,10 @@ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index f8c2c351e5a..8d9881eadeb 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
-@@ -61,11 +61,3 @@ along with GCC; see the file COPYING3.  If not see
-     %{static:-static}}"
- 
- #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+@@ -60,11 +60,3 @@ along with GCC; see the file COPYING3.  If not see
+ 	%{rdynamic:-export-dynamic} \
+ 	-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
 -
 -#define STARTFILE_PREFIX_SPEC 			\
 -   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\

cross/gcc-x86/0026-ada-musl-support-fixes.patch

@@ -41,6 +41,15 @@ index 96306f8cc9a..090b6770ae5 100644
    LIBGNAT_TARGET_PAIRS = \
    a-intnam.ads<libgnarl/a-intnam__linux.ads \
    s-inmaop.adb<libgnarl/s-inmaop__posix.adb \
+@@ -2311,7 +2311,7 @@ ifeq ($(strip $(filter-out aarch64% linux%,$(target_cpu) $(target_os))),)
+   s-intman.adb<libgnarl/s-intman__posix.adb \
+   s-linux.ads<libgnarl/s-linux.ads \
+   $(TRASYM_DWARF_UNIX_PAIRS) \
+-  s-tsmona.adb<libgnat/s-tsmona__linux.adb \
++  s-tsmona.adb<libgnat/s-tsmona.adb \
+   s-mudido.adb<libgnarl/s-mudido__affinity.adb \
+   s-osinte.ads<libgnarl/s-osinte__linux.ads \
+   s-osinte.adb<libgnarl/s-osinte__posix.adb \
 @@ -2420,7 +2420,7 @@ ifeq ($(strip $(filter-out %ia64 linux%,$(target_cpu) $(target_os))),)
    s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \
    s-taspri.ads<libgnarl/s-taspri__posix-noaltstack.ads \

cross/gcc-x86/0035-loongarch-disable-multilib-support.patch

@@ -0,0 +1,32 @@
+From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 7 Aug 2023 15:25:58 +0800
+Subject: [PATCH] loongarch disable multilib support
+
+Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
+---
+ gcc/config/loongarch/t-linux    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 23e1fb979..c2753abb8 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -21,11 +21,6 @@ MULTIOSDIR_lp64f := ../lib64/f32$(call if_multiarch,:loongarch64-linux-gnuf32)
+ MULTIOSDIR_lp64s := ../lib64/sf$(call if_multiarch,:loongarch64-linux-gnusf)
+ 
+ # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
+-ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+-
+-    MULTILIB_OSDIRNAMES = .=$(MULTIOSDIR_$(mlib_default))
+-    MULTILIB_OSDIRNAMES += mabi.lp64d=$(MULTIOSDIR_lp64d)
+-    MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+-    MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+-
+-endif
++    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
+-- 
+2.41.0
+

cross/gcc-x86/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-x86/0037-loongarch-disable-multilib-support.patch

@@ -1,61 +0,0 @@
-From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
-From: Jingyun Hua <huajingyun@loongson.cn>
-Date: Mon, 7 Aug 2023 15:25:58 +0800
-Subject: [PATCH] loongarch disable multilib support
-
-Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
----
- gcc/config/loongarch/linux.h    | 10 +---------
- gcc/config/loongarch/t-linux    | 18 +++---------------
- 3 files changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
-index 9059d2441..23eaff0cc 100644
---- a/gcc/config/loongarch/linux.h
-+++ b/gcc/config/loongarch/linux.h
-@@ -22,15 +22,7 @@ along with GCC; see the file COPYING3.  If not see
-  * can work in a multilib environment.  */
- 
- #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
--
--  #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
--    #define ABI_LIBDIR "lib64"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
--    #define ABI_LIBDIR "lib64/f32"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64S
--    #define ABI_LIBDIR "lib64/sf"
--  #endif
--
-+    #define ABI_LIBDIR "lib"
- #endif
- 
- #ifndef ABI_LIBDIR
-diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
-index e40da1792..f72c6e878 100644
---- a/gcc/config/loongarch/t-linux
-+++ b/gcc/config/loongarch/t-linux
-@@ -36,18 +36,6 @@ else
- endif
- 
- # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
--ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
--
--    MULTILIB_OSDIRNAMES = \
--      mabi.lp64d=../lib64$\
--      $(call if_multiarch,:loongarch64-linux-gnu)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64f=../lib64/f32$\
--      $(call if_multiarch,:loongarch64-linux-gnuf32)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64s=../lib64/sf$\
--      $(call if_multiarch,:loongarch64-linux-gnusf)
--
--endif
-+    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
--- 
-2.41.0
-

cross/gcc-x86/APKBUILD

@@ -24,7 +24,7 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-x86
-pkgver=13.2.1_git20240309
+pkgver=14.2.0
 # i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-x86
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for x86"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -171,7 +171,7 @@ esac
 # currently on x86, x86_64 and ia64
 _libquadmath=$LANG_FORTRAN
 case "$CTARGET_ARCH" in
-x86 | x86_64 | ppc64le)	_libquadmath=$LANG_FORTRAN ;;
+x86 | x86_64)	_libquadmath=$LANG_FORTRAN ;;
 *)		_libquadmath=false ;;
 esac
 
@@ -241,7 +241,8 @@ makedepends="$makedepends_build $makedepends_host"
 #
 # PLEASE submit all patches to gcc to https://gitlab.alpinelinux.org/kaniini/alpine-gcc-patches,
 # so that they can be properly tracked and easily rebased if needed.
-source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+#source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkgbase:-$pkgver}.tar.xz
 	0001-posix_memalign.patch
 	0002-gcc-poison-system-directories.patch
 	0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -276,8 +277,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-	0037-loongarch-disable-multilib-support.patch
+	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -285,7 +286,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 #     - CVE-2023-4039
 
 # we build out-of-tree
-_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+#_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+_gccdir="$srcdir"/gcc-${_pkgbase:-$pkgver}
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 _gcclibexec="/usr/libexec/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 
@@ -364,7 +366,14 @@ build() {
 	$_libgomp	|| _bootstrap_configure="$_bootstrap_configure --disable-libgomp"
 	$_libatomic	|| _bootstrap_configure="$_bootstrap_configure --disable-libatomic"
 	$_libitm	|| _bootstrap_configure="$_bootstrap_configure --disable-libitm"
-	$_libquadmath	|| _arch_configure="$_arch_configure --disable-libquadmath"
+	if ! $_libquadmath; then
+		_arch_configure="$_arch_configure --disable-libquadmath"
+		# ppc64le needs both --disable-libquadmath{,-support}
+		# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116007
+		[ "$CARCH" = "ppc64le" ] &&
+			_arch_configure="$_arch_configure
+				--disable-libquadmath-support"
+	fi
 
 	msg "Building the following:"
 	echo ""
@@ -793,9 +802,9 @@ gdb() {
 }
 
 sha512sums="
-2d1e0374ebdee526f0549319fc9c364968c52a0d4aaa16759f00453cb083fe58d8f463c47d97f3bb74a0a92e251989eb75a50ee5800b4569978c72d25446b44e  gcc-13-20240309.tar.xz
+932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396  gcc-14.2.0.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
-163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
+1d102a7b17683909dde4d8591dd889149299e77a2b2003cdc0635dc816666be940e41ae534b469485391a9bed183cd5cd337f130e4e1ecb62cb9ad86c4a081db  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
 17a2993027d3ddf8595952ebcae425695ddc7b1cf73b384d2e55fddecb9cbf3f6482860a502ff69b14075e12badf27300fd3039f3a9005e851fd8d121d258c2b  0004-Turn-on-D_FORTIFY_SOURCE-2-by-default-for-C-C-ObjC-O.patch
 444550e55491ff89fe8cbbb4b73d017c9c147cdce1ad5c0561fe7d6ab3834515a814c7676c408cfeec18e1aaace27b3c26a2ffe4a75042285df5124976c38672  0005-On-linux-targets-pass-as-needed-by-default-to-the-li.patch
@@ -806,7 +815,7 @@ sha512sums="
 da9eaf2f0ddbec5ee14dc26053936587e6c76fbf16846db804a18cf4d318579426ebcc566aed02daf8e34f60c08b61f5d3959305886dca9bbcdc84db057258d9  0010-Don-t-declare-asprintf-if-defined-as-a-macro.patch
 35b9aafe7eee8138cb7aad7164a8f77c15ccdce26843cee78b5871ef91d76cad22ed0871b20f51c4b89b71afd9cfe4ba4227086e158c466558513708fe7d2a1a  0011-libiberty-copy-PIC-objects-during-build-process.patch
 9d43f844fad0ac6e1c35a2b6f461f9278ae09e468f2c9ae8adc43accbe6934994aa10d3a433644d1393a4a76e3caed69e3191db7f3c0c24b4e7a0a0a0cbac3f1  0012-libgcc_s.patch
-b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e45334290dbe467a4e891ed34a6522e0c72f746def22e8663  0013-nopie.patch
+91dde3079c1400c124ab5604597f5857185d075809649603aa3641a4581b34029bfcbd4281a5bd925d1c5e6e3b1f5f3322efda34345c6930652d685a6c9525f4  0013-nopie.patch
 0b50ad15115192699efa9fda3d4fb1c2fa95da06d7880ba34615b40c19a8256e1fe364da39f5c70dc22fbccf21db2de5900932afef68948722eeb25e435262f8  0014-ada-fix-shared-linking.patch
 00097c7106625ccf02149a757366f434c48f2abe824bb8b4bf067d29308889cb6039a5e5b2d3bd2683617693b47707d549252c56eea6bc3cdc2450a8d14f46a7  0015-build-fix-CXXFLAGS_FOR_BUILD-passing.patch
 7f0bc42b93a389b614054e700b851abfbc53db391aa10cbdf6990d41396b293af78980bb39f1cf0967184d3fbf3d46ac7c7f096717b8f193ea34cbf7f37d7e91  0016-add-fortify-headers-paths.patch
@@ -816,10 +825,10 @@ b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e
 a9567947471c3ba8a547a79c55e183974554bf823d9a97a165c966d7b3caad8789980e096e3b78452ece5de062bd9bb006af464bbf0c5a35b689eac3ee21e5c5  0020-s390x-disable-multilib-support.patch
 f382eb5f7c2c60c5a23fac587c9629a3059d7be0898e97a1feaf9b9cbe1ef4693cc1177eb29333e8b7944fa17487478e73958be45d5782ccb9ef501961fb9a96  0021-ppc64-le-disable-multilib-support.patch
 44ab86feb8e41e7c2b2e27accdf46194c9b80ee6a39543303dc04824f669d9fad182aabd40c9c7f6c265cf9bb71be830c257be115dc9d701d54eca3aa9ef174e  0022-x86_64-disable-multilib-support.patch
-e0763083c31485e8ac0b3724376a28af01bb6f50e1a054780b61886e4e3de2a35d127e6e353eb8d8729964ada9b5751bf05bdd51df539667008216db38f228a3  0023-riscv-disable-multilib-support.patch
+abf845792433a21fed5dd06167b9f6cf5e8f8026a409acce93824e466c5148e192bf5f404a271931fe4b65283499329bf67bb01019f2f3e02501f20619404e6c  0023-riscv-disable-multilib-support.patch
 ab88a2f63e3545bbc36537aa9a86f2c6c35e41bbf702d6e13743a405cdac4f901eed5737189b780da96647fea9f5d863fdc76373f25a00064106dcb5514d6d87  0024-always-build-libgcc_eh.a.patch
 8fdbe0c8bf4ca60f458a33e59027de03d15ac91933fe46d8ca62119346d20b9bc2447c0bf22bceb63d0cf8613ab61512d9197f4e6c2224af473b63ef9f254295  0025-ada-libgnarl-compatibility-for-musl.patch
-30369bea84020c32d514196ba3adb3d09d2d0359af5550bd3f9719aa357e44b2f695623c1d2a99416e120dc86896c196c5dd4f638183dced4799604137385367  0026-ada-musl-support-fixes.patch
+5fd23a506b55c88d4f000e01c539eb25d6da2516949c9d7a1c9ee20f4c6b627e4788541284d9c14c33bafa7cb43ce2e0469dd91006152f00e30815107150320f  0026-ada-musl-support-fixes.patch
 3f9a406d7d2ce34951215ffbcadb49a45e55ad5c24ab9097c0e5e92383e43b876872ccd2a7e7def2833ab204975ee5733f8bcf90934db9fa9c4f6f56c62081f6  0027-configure-Add-enable-autolink-libatomic-use-in-LINK_.patch
 720a4001f9a1fa4122e456077ecff8d3eb8af7c83d0a81f9da6a6cca05b23664206a82a349e34482c48bfe40e99aa5f21567613d0913f6a24f282bc84a994496  0028-configure-fix-detection-of-atomic-builtins-in-libato.patch
 2044c23b23726965c0a6fd39f616cc464badd650947cb40495eeabd906a3af629878c1d28b403b8eb46b30a1a0ba39083023290d62f0c99ccf070063226e3f8f  0029-libstdc-do-not-throw-exceptions-for-non-C-locales-on.patch
@@ -828,6 +837,6 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-d834f5f95f4ebe70ec0af0748c8632c99a4f57b69dc14db1a38becdfcb03406b32febf39f772f37bd145538147099fa7433edce845e14ee77cd8f38fd9774fc1  0037-loongarch-disable-multilib-support.patch
+65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-x86/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/gcc-x86_64/0002-gcc-poison-system-directories.patch

@@ -150,13 +150,13 @@ diff --git a/gcc/gcc.cc b/gcc/gcc.cc
 index 16bb07f2cdc..33b56e721d2 100644
 --- a/gcc/gcc.cc
 +++ b/gcc/gcc.cc
-@@ -1146,6 +1146,8 @@ proper position among the other output files.  */
-    "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
+@@ -1177,6 +1187,8 @@ proper position among the other output files.  */
+    "-z now " \
     "%X %{o*} %{e*} %{N} %{n} %{r}\
      %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
 +    %{Wno-poison-system-directories:--no-poison-system-directories} \
 +    %{Werror=poison-system-directories:--error-poison-system-directories} \
-     %{static|no-pie|static-pie:} %@{L*} %(mfwrap) %(link_libgcc) " \
+     %{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
      VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o "" \
      %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
 diff --git a/gcc/incpath.cc b/gcc/incpath.cc

cross/gcc-x86_64/0013-nopie.patch

@@ -9,23 +9,22 @@ Subject: [PATCH 13/35] nopie
  2 files changed, 40 insertions(+)
 
 diff --git a/gcc/configure b/gcc/configure
-index 8c46369f73f..e59cbee1767 100755
+index 23da7d55d..f38732bb2 100755
 --- a/gcc/configure
 +++ b/gcc/configure
-@@ -32268,6 +32268,33 @@ fi
+@@ -34534,6 +34534,29 @@ rm -f core conftest.err conftest.$ac_objext \
+ fi
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie" >&5
  $as_echo "$gcc_cv_no_pie" >&6; }
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
++# Check if -nopie works.
++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for -nopie option" >&5
 +$as_echo_n "checking for -nopie option... " >&6; }
-+if test "${gcc_cv_nopie+set}" = set; then :
++if ${gcc_cv_nopie+:} false; then :
 +  $as_echo_n "(cached) " >&6
 +else
 +  saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++   LDFLAGS="$LDFLAGS -nopie"
++   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 +/* end confdefs.h.  */
 +int main(void) {return 0;}
 +_ACEOF
@@ -36,40 +35,51 @@ index 8c46369f73f..e59cbee1767 100755
 +fi
 +rm -f core conftest.err conftest.$ac_objext \
 +    conftest$ac_exeext conftest.$ac_ext
-+     LDFLAGS="$saved_LDFLAGS"
++   LDFLAGS="$saved_LDFLAGS"
 +fi
 +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_nopie" >&5
 +$as_echo "$gcc_cv_nopie" >&6; }
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
+ 
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -34551,6 +34574,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
  fi
- 
- 
 diff --git a/gcc/configure.ac b/gcc/configure.ac
-index 5504bf6eb01..57268319de1 100644
+index d7cf0b92c..db2e2c802 100644
 --- a/gcc/configure.ac
 +++ b/gcc/configure.ac
-@@ -7552,6 +7552,19 @@ AC_CACHE_CHECK([for -no-pie option],
+@@ -7781,6 +7781,15 @@ AC_CACHE_CHECK([for -no-pie option],
+      [gcc_cv_no_pie=yes],
+      [gcc_cv_no_pie=no])
     LDFLAGS="$saved_LDFLAGS"])
- if test "$gcc_cv_no_pie" = "yes"; then
-   NO_PIE_FLAG="-no-pie"
-+else
-+  # Check if -nopie works.
-+  AC_CACHE_CHECK([for -nopie option],
-+    [gcc_cv_nopie],
-+    [saved_LDFLAGS="$LDFLAGS"
-+     LDFLAGS="$LDFLAGS -nopie"
-+     AC_LINK_IFELSE([int main(void) {return 0;}],
-+       [gcc_cv_nopie=yes],
-+       [gcc_cv_nopie=no])
-+     LDFLAGS="$saved_LDFLAGS"])
-+  if test "$gcc_cv_nopie" = "yes"; then
-+    NO_PIE_FLAG="-nopie"
-+  fi
- fi
- AC_SUBST([NO_PIE_FLAG])
++# Check if -nopie works.
++AC_CACHE_CHECK([for -nopie option],
++  [gcc_cv_nopie],
++  [saved_LDFLAGS="$LDFLAGS"
++   LDFLAGS="$LDFLAGS -nopie"
++   AC_LINK_IFELSE([AC_LANG_SOURCE([int main(void) {return 0;}])],
++     [gcc_cv_nopie=yes],
++     [gcc_cv_nopie=no])
++   LDFLAGS="$saved_LDFLAGS"])
  
+ if test x$enable_host_shared = xyes; then
+   PICFLAG=-fPIC
+@@ -7798,6 +7807,8 @@ if test x$enable_host_pie = xyes; then
+   LD_PICFLAG=-pie
+ elif test x$gcc_cv_no_pie = xyes; then
+   LD_PICFLAG=-no-pie
++elif test x$gcc_cv_nopie = xyes; then
++  LD_PICFLAG=-nopie
+ else
+   LD_PICFLAG=
+ fi
 -- 
 2.41.0
 

cross/gcc-x86_64/0023-riscv-disable-multilib-support.patch

@@ -46,10 +46,10 @@ diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
 index f8c2c351e5a..8d9881eadeb 100644
 --- a/gcc/config/riscv/linux.h
 +++ b/gcc/config/riscv/linux.h
-@@ -61,11 +61,3 @@ along with GCC; see the file COPYING3.  If not see
-     %{static:-static}}"
- 
- #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+@@ -60,11 +60,3 @@ along with GCC; see the file COPYING3.  If not see
+ 	%{rdynamic:-export-dynamic} \
+ 	-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
+     %{static:-static} %{static-pie:-static -pie --no-dynamic-linker -z text}}"
 -
 -#define STARTFILE_PREFIX_SPEC 			\
 -   "/lib" XLEN_SPEC "/" ABI_SPEC "/ "		\

cross/gcc-x86_64/0026-ada-musl-support-fixes.patch

@@ -41,6 +41,15 @@ index 96306f8cc9a..090b6770ae5 100644
    LIBGNAT_TARGET_PAIRS = \
    a-intnam.ads<libgnarl/a-intnam__linux.ads \
    s-inmaop.adb<libgnarl/s-inmaop__posix.adb \
+@@ -2311,7 +2311,7 @@ ifeq ($(strip $(filter-out aarch64% linux%,$(target_cpu) $(target_os))),)
+   s-intman.adb<libgnarl/s-intman__posix.adb \
+   s-linux.ads<libgnarl/s-linux.ads \
+   $(TRASYM_DWARF_UNIX_PAIRS) \
+-  s-tsmona.adb<libgnat/s-tsmona__linux.adb \
++  s-tsmona.adb<libgnat/s-tsmona.adb \
+   s-mudido.adb<libgnarl/s-mudido__affinity.adb \
+   s-osinte.ads<libgnarl/s-osinte__linux.ads \
+   s-osinte.adb<libgnarl/s-osinte__posix.adb \
 @@ -2420,7 +2420,7 @@ ifeq ($(strip $(filter-out %ia64 linux%,$(target_cpu) $(target_os))),)
    s-tpopsp.adb<libgnarl/s-tpopsp__tls.adb \
    s-taspri.ads<libgnarl/s-taspri__posix-noaltstack.ads \

cross/gcc-x86_64/0035-loongarch-disable-multilib-support.patch

@@ -0,0 +1,32 @@
+From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 7 Aug 2023 15:25:58 +0800
+Subject: [PATCH] loongarch disable multilib support
+
+Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
+---
+ gcc/config/loongarch/t-linux    | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
+index 23e1fb979..c2753abb8 100644
+--- a/gcc/config/loongarch/t-linux
++++ b/gcc/config/loongarch/t-linux
+@@ -21,11 +21,6 @@ MULTIOSDIR_lp64f := ../lib64/f32$(call if_multiarch,:loongarch64-linux-gnuf32)
+ MULTIOSDIR_lp64s := ../lib64/sf$(call if_multiarch,:loongarch64-linux-gnusf)
+ 
+ # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
+-ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+-
+-    MULTILIB_OSDIRNAMES = .=$(MULTIOSDIR_$(mlib_default))
+-    MULTILIB_OSDIRNAMES += mabi.lp64d=$(MULTIOSDIR_lp64d)
+-    MULTILIB_OSDIRNAMES += mabi.lp64f=$(MULTIOSDIR_lp64f)
+-    MULTILIB_OSDIRNAMES += mabi.lp64s=$(MULTIOSDIR_lp64s)
+-
+-endif
++    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
++    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
+-- 
+2.41.0
+

cross/gcc-x86_64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

@@ -1,186 +0,0 @@
-https://gcc.gnu.org/PR110792
-https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
-https://github.com/randombit/botan/issues/3637
-
-From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
-From: Roger Sayle <roger@nextmovesoftware.com>
-Date: Thu, 3 Aug 2023 07:12:04 +0100
-Subject: [PATCH] PR target/110792: Early clobber issues with
- rot32di2_doubleword on i386.
-
-This patch is a conservative fix for PR target/110792, a wrong-code
-regression affecting doubleword rotations by BITS_PER_WORD, which
-effectively swaps the highpart and lowpart words, when the source to be
-rotated resides in memory. The issue is that if the register used to
-hold the lowpart of the destination is mentioned in the address of
-the memory operand, the current define_insn_and_split unintentionally
-clobbers it before reading the highpart.
-
-Hence, for the testcase, the incorrectly generated code looks like:
-
-        salq    $4, %rdi		// calculate address
-        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
-        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
-
-Traditionally, the textbook way to fix this would be to add an
-explicit early clobber to the instruction's constraints.
-
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
-        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-                       (const_int 32)))]
-
-but unfortunately this currently generates significantly worse code,
-due to a strange choice of reloads (effectively memcpy), which ends up
-looking like:
-
-        salq    $4, %rdi		// calculate address
-        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
-        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
-        movq    -8(%rsp), %rdi		// load highpart
-        movq    -16(%rsp), %rbp		// load lowpart
-
-Note that reload's "&" doesn't distinguish between the memory being
-early clobbered, vs the registers used in an addressing mode being
-early clobbered.
-
-The fix proposed in this patch is to remove the third alternative, that
-allowed offsetable memory as an operand, forcing reload to place the
-operand into a register before the rotation.  This results in:
-
-        salq    $4, %rdi
-        movq    WHIRL_S(%rdi), %rax
-        movq    WHIRL_S+8(%rdi), %rdi
-        movq    %rax, %rbp
-
-I believe there's a more advanced solution, by swapping the order of
-the loads (if first destination register is mentioned in the address),
-or inserting a lea insn (if both destination registers are mentioned
-in the address), but this fix is a minimal "safe" solution, that
-should hopefully be suitable for backporting.
-
-2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
-
-gcc/ChangeLog
-	PR target/110792
-	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
-	place operand in a register before gen_<insn>64ti2_doubleword.
-	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
-	operand in a register before gen_<insn>32di2_doubleword.
-	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
-	(<any_rotate>64ti2_doubleword): Likewise.
-
-gcc/testsuite/ChangeLog
-	PR target/110792
-	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
-	* gcc.target/i386/pr110792.c: New 64-bit C test case.
-
-(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
----
- gcc/config/i386/i386.md                  | 18 ++++++++++++------
- gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
- gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
- 3 files changed, 46 insertions(+), 6 deletions(-)
- create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
- create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
-
-diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
-index f3a3305..a71e837 100644
---- a/gcc/config/i386/i386.md
-+++ b/gcc/config/i386/i386.md
-@@ -14359,7 +14359,10 @@
-     emit_insn (gen_ix86_<insn>ti3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
--    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (TImode, operands[1]);
-+      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     {
-       rtx amount = force_reg (QImode, operands[2]);
-@@ -14394,7 +14397,10 @@
-     emit_insn (gen_ix86_<insn>di3_doubleword
- 		(operands[0], operands[1], operands[2]));
-   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
--    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    {
-+      operands[1] = force_reg (DImode, operands[1]);
-+      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
-+    }
-   else
-     FAIL;
- 
-@@ -14562,8 +14568,8 @@
- })
- 
- (define_insn_and_split "<insn>32di2_doubleword"
-- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
--       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:DI 0 "register_operand" "=r,r")
-+       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
-                       (const_int 32)))]
-  "!TARGET_64BIT"
-  "#"
-@@ -14580,8 +14586,8 @@
- })
- 
- (define_insn_and_split "<insn>64ti2_doubleword"
-- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
--       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
-+ [(set (match_operand:TI 0 "register_operand" "=r,r")
-+       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
-                       (const_int 64)))]
-  "TARGET_64BIT"
-  "#"
-diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
-new file mode 100644
-index 0000000..ce21a7a
---- /dev/null
-+++ b/gcc/testsuite/g++.target/i386/pr110792.C
-@@ -0,0 +1,16 @@
-+/* { dg-do compile { target ia32 } } */
-+/* { dg-options "-O2" } */
-+
-+template <int ROT, typename T>
-+inline T rotr(T input)
-+{
-+   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
-+}
-+
-+unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
-+unsigned long long whirl(unsigned char x0)
-+{
-+   const unsigned long long s4 = WHIRL_S[x0&0xFF];
-+   return rotr<32>(s4);
-+}
-+/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
-diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
-new file mode 100644
-index 0000000..b65125c
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/i386/pr110792.c
-@@ -0,0 +1,18 @@
-+/* { dg-do compile { target int128 } } */
-+/* { dg-options "-O2" } */
-+
-+static inline unsigned __int128 rotr(unsigned __int128 input)
-+{
-+   return ((input >> 64) | (input << (64)));
-+}
-+
-+unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
-+unsigned __int128 whirl(unsigned char x0)
-+{
-+   register int t __asm("rdi") = x0&0xFF;
-+   const unsigned __int128 s4 = WHIRL_S[t];
-+   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
-+   asm("":::"memory");
-+   return tt;
-+}
-+/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
--- 
-2.41.0
-

cross/gcc-x86_64/0037-loongarch-disable-multilib-support.patch

@@ -1,61 +0,0 @@
-From c4f484f465a32e796ae384aa3f90e79fa218b4e9 Mon Sep 17 00:00:00 2001
-From: Jingyun Hua <huajingyun@loongson.cn>
-Date: Mon, 7 Aug 2023 15:25:58 +0800
-Subject: [PATCH] loongarch disable multilib support
-
-Signed-off-by: Jingyun Hua <huajingyun@loongson.cn>
----
- gcc/config/loongarch/linux.h    | 10 +---------
- gcc/config/loongarch/t-linux    | 18 +++---------------
- 3 files changed, 5 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
-index 9059d2441..23eaff0cc 100644
---- a/gcc/config/loongarch/linux.h
-+++ b/gcc/config/loongarch/linux.h
-@@ -22,15 +22,7 @@ along with GCC; see the file COPYING3.  If not see
-  * can work in a multilib environment.  */
- 
- #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
--
--  #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
--    #define ABI_LIBDIR "lib64"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
--    #define ABI_LIBDIR "lib64/f32"
--  #elif DEFAULT_ABI_BASE == ABI_BASE_LP64S
--    #define ABI_LIBDIR "lib64/sf"
--  #endif
--
-+    #define ABI_LIBDIR "lib"
- #endif
- 
- #ifndef ABI_LIBDIR
-diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
-index e40da1792..f72c6e878 100644
---- a/gcc/config/loongarch/t-linux
-+++ b/gcc/config/loongarch/t-linux
-@@ -36,18 +36,6 @@ else
- endif
- 
- # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
--ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
--
--    MULTILIB_OSDIRNAMES = \
--      mabi.lp64d=../lib64$\
--      $(call if_multiarch,:loongarch64-linux-gnu)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64f=../lib64/f32$\
--      $(call if_multiarch,:loongarch64-linux-gnuf32)
--
--    MULTILIB_OSDIRNAMES += \
--      mabi.lp64s=../lib64/sf$\
--      $(call if_multiarch,:loongarch64-linux-gnusf)
--
--endif
-+    MULTILIB_OSDIRNAMES =  mabi.lp64d=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64f=../lib
-+    MULTILIB_OSDIRNAMES += mabi.lp64s=../lib
--- 
-2.41.0
-

cross/gcc-x86_64/APKBUILD

@@ -24,7 +24,7 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-x86_64
-pkgver=13.2.1_git20240309
+pkgver=14.2.0
 # i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-x86_64
-pkgrel=0
+pkgrel=1
 pkgdesc="Stage2 cross-compiler for x86_64"
 url="https://gcc.gnu.org"
 arch="aarch64"
@@ -171,7 +171,7 @@ esac
 # currently on x86, x86_64 and ia64
 _libquadmath=$LANG_FORTRAN
 case "$CTARGET_ARCH" in
-x86 | x86_64 | ppc64le)	_libquadmath=$LANG_FORTRAN ;;
+x86 | x86_64)	_libquadmath=$LANG_FORTRAN ;;
 *)		_libquadmath=false ;;
 esac
 
@@ -241,7 +241,8 @@ makedepends="$makedepends_build $makedepends_host"
 #
 # PLEASE submit all patches to gcc to https://gitlab.alpinelinux.org/kaniini/alpine-gcc-patches,
 # so that they can be properly tracked and easily rebased if needed.
-source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+#source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${_pkgbase%%.*}-$_pkgsnap.tar.xz
+source="https://gcc.gnu.org/pub/gcc/releases/gcc-${_pkgbase:-$pkgver}/gcc-${_pkgbase:-$pkgver}.tar.xz
 	0001-posix_memalign.patch
 	0002-gcc-poison-system-directories.patch
 	0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -276,8 +277,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-	0037-loongarch-disable-multilib-support.patch
+	0035-loongarch-disable-multilib-support.patch
+	fix-arm64.patch
 	"
 
 # secfixes:
@@ -285,7 +286,8 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 #     - CVE-2023-4039
 
 # we build out-of-tree
-_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+#_gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
+_gccdir="$srcdir"/gcc-${_pkgbase:-$pkgver}
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 _gcclibexec="/usr/libexec/gcc/$CTARGET/${_pkgbase:-$pkgver}"
 
@@ -364,7 +366,14 @@ build() {
 	$_libgomp	|| _bootstrap_configure="$_bootstrap_configure --disable-libgomp"
 	$_libatomic	|| _bootstrap_configure="$_bootstrap_configure --disable-libatomic"
 	$_libitm	|| _bootstrap_configure="$_bootstrap_configure --disable-libitm"
-	$_libquadmath	|| _arch_configure="$_arch_configure --disable-libquadmath"
+	if ! $_libquadmath; then
+		_arch_configure="$_arch_configure --disable-libquadmath"
+		# ppc64le needs both --disable-libquadmath{,-support}
+		# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116007
+		[ "$CARCH" = "ppc64le" ] &&
+			_arch_configure="$_arch_configure
+				--disable-libquadmath-support"
+	fi
 
 	msg "Building the following:"
 	echo ""
@@ -793,9 +802,9 @@ gdb() {
 }
 
 sha512sums="
-2d1e0374ebdee526f0549319fc9c364968c52a0d4aaa16759f00453cb083fe58d8f463c47d97f3bb74a0a92e251989eb75a50ee5800b4569978c72d25446b44e  gcc-13-20240309.tar.xz
+932bdef0cda94bacedf452ab17f103c0cb511ff2cec55e9112fc0328cbf1d803b42595728ea7b200e0a057c03e85626f937012e49a7515bc5dd256b2bf4bc396  gcc-14.2.0.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
-163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
+1d102a7b17683909dde4d8591dd889149299e77a2b2003cdc0635dc816666be940e41ae534b469485391a9bed183cd5cd337f130e4e1ecb62cb9ad86c4a081db  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
 17a2993027d3ddf8595952ebcae425695ddc7b1cf73b384d2e55fddecb9cbf3f6482860a502ff69b14075e12badf27300fd3039f3a9005e851fd8d121d258c2b  0004-Turn-on-D_FORTIFY_SOURCE-2-by-default-for-C-C-ObjC-O.patch
 444550e55491ff89fe8cbbb4b73d017c9c147cdce1ad5c0561fe7d6ab3834515a814c7676c408cfeec18e1aaace27b3c26a2ffe4a75042285df5124976c38672  0005-On-linux-targets-pass-as-needed-by-default-to-the-li.patch
@@ -806,7 +815,7 @@ sha512sums="
 da9eaf2f0ddbec5ee14dc26053936587e6c76fbf16846db804a18cf4d318579426ebcc566aed02daf8e34f60c08b61f5d3959305886dca9bbcdc84db057258d9  0010-Don-t-declare-asprintf-if-defined-as-a-macro.patch
 35b9aafe7eee8138cb7aad7164a8f77c15ccdce26843cee78b5871ef91d76cad22ed0871b20f51c4b89b71afd9cfe4ba4227086e158c466558513708fe7d2a1a  0011-libiberty-copy-PIC-objects-during-build-process.patch
 9d43f844fad0ac6e1c35a2b6f461f9278ae09e468f2c9ae8adc43accbe6934994aa10d3a433644d1393a4a76e3caed69e3191db7f3c0c24b4e7a0a0a0cbac3f1  0012-libgcc_s.patch
-b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e45334290dbe467a4e891ed34a6522e0c72f746def22e8663  0013-nopie.patch
+91dde3079c1400c124ab5604597f5857185d075809649603aa3641a4581b34029bfcbd4281a5bd925d1c5e6e3b1f5f3322efda34345c6930652d685a6c9525f4  0013-nopie.patch
 0b50ad15115192699efa9fda3d4fb1c2fa95da06d7880ba34615b40c19a8256e1fe364da39f5c70dc22fbccf21db2de5900932afef68948722eeb25e435262f8  0014-ada-fix-shared-linking.patch
 00097c7106625ccf02149a757366f434c48f2abe824bb8b4bf067d29308889cb6039a5e5b2d3bd2683617693b47707d549252c56eea6bc3cdc2450a8d14f46a7  0015-build-fix-CXXFLAGS_FOR_BUILD-passing.patch
 7f0bc42b93a389b614054e700b851abfbc53db391aa10cbdf6990d41396b293af78980bb39f1cf0967184d3fbf3d46ac7c7f096717b8f193ea34cbf7f37d7e91  0016-add-fortify-headers-paths.patch
@@ -816,10 +825,10 @@ b2c4921c5eef33ee43a92ab5ec7f09d5d3adb49a2416595001e6376ffdf652ef9d0dc21778c3a86e
 a9567947471c3ba8a547a79c55e183974554bf823d9a97a165c966d7b3caad8789980e096e3b78452ece5de062bd9bb006af464bbf0c5a35b689eac3ee21e5c5  0020-s390x-disable-multilib-support.patch
 f382eb5f7c2c60c5a23fac587c9629a3059d7be0898e97a1feaf9b9cbe1ef4693cc1177eb29333e8b7944fa17487478e73958be45d5782ccb9ef501961fb9a96  0021-ppc64-le-disable-multilib-support.patch
 44ab86feb8e41e7c2b2e27accdf46194c9b80ee6a39543303dc04824f669d9fad182aabd40c9c7f6c265cf9bb71be830c257be115dc9d701d54eca3aa9ef174e  0022-x86_64-disable-multilib-support.patch
-e0763083c31485e8ac0b3724376a28af01bb6f50e1a054780b61886e4e3de2a35d127e6e353eb8d8729964ada9b5751bf05bdd51df539667008216db38f228a3  0023-riscv-disable-multilib-support.patch
+abf845792433a21fed5dd06167b9f6cf5e8f8026a409acce93824e466c5148e192bf5f404a271931fe4b65283499329bf67bb01019f2f3e02501f20619404e6c  0023-riscv-disable-multilib-support.patch
 ab88a2f63e3545bbc36537aa9a86f2c6c35e41bbf702d6e13743a405cdac4f901eed5737189b780da96647fea9f5d863fdc76373f25a00064106dcb5514d6d87  0024-always-build-libgcc_eh.a.patch
 8fdbe0c8bf4ca60f458a33e59027de03d15ac91933fe46d8ca62119346d20b9bc2447c0bf22bceb63d0cf8613ab61512d9197f4e6c2224af473b63ef9f254295  0025-ada-libgnarl-compatibility-for-musl.patch
-30369bea84020c32d514196ba3adb3d09d2d0359af5550bd3f9719aa357e44b2f695623c1d2a99416e120dc86896c196c5dd4f638183dced4799604137385367  0026-ada-musl-support-fixes.patch
+5fd23a506b55c88d4f000e01c539eb25d6da2516949c9d7a1c9ee20f4c6b627e4788541284d9c14c33bafa7cb43ce2e0469dd91006152f00e30815107150320f  0026-ada-musl-support-fixes.patch
 3f9a406d7d2ce34951215ffbcadb49a45e55ad5c24ab9097c0e5e92383e43b876872ccd2a7e7def2833ab204975ee5733f8bcf90934db9fa9c4f6f56c62081f6  0027-configure-Add-enable-autolink-libatomic-use-in-LINK_.patch
 720a4001f9a1fa4122e456077ecff8d3eb8af7c83d0a81f9da6a6cca05b23664206a82a349e34482c48bfe40e99aa5f21567613d0913f6a24f282bc84a994496  0028-configure-fix-detection-of-atomic-builtins-in-libato.patch
 2044c23b23726965c0a6fd39f616cc464badd650947cb40495eeabd906a3af629878c1d28b403b8eb46b30a1a0ba39083023290d62f0c99ccf070063226e3f8f  0029-libstdc-do-not-throw-exceptions-for-non-C-locales-on.patch
@@ -828,6 +837,6 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
-d834f5f95f4ebe70ec0af0748c8632c99a4f57b69dc14db1a38becdfcb03406b32febf39f772f37bd145538147099fa7433edce845e14ee77cd8f38fd9774fc1  0037-loongarch-disable-multilib-support.patch
+65df1d489e8d07a811f39e27fd29e3b2b4164fbc2c5fdc16a5142886d94a96e3fb28ccf4f20dd297ba6540ef8ea1ac3eb65a4279494639bf2f0f8376a3896cc3  0035-loongarch-disable-multilib-support.patch
+00319c9770362520e8e93bd03fda1769dfa3622eba77d620e11d8af45a38e6d804a5e924046ae388e1cfaea605696e89c343fca507aaaa5edd58d80744fff14f  fix-arm64.patch
 "

cross/gcc-x86_64/fix-arm64.patch

@@ -0,0 +1,544 @@
+From 2894660df1292153632edbc2a5b66eaf6a864660 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Thu, 13 Jun 2024 12:48:21 +0100
+Subject: [PATCH 1/4] aarch64: Fix invalid nested subregs [PR115464]
+
+The testcase extracts one arm_neon.h vector from a pair (one subreg)
+and then reinterprets the result as an SVE vector (another subreg).
+Each subreg makes sense individually, but we can't fold them together
+into a single subreg: it's 32 bytes -> 16 bytes -> 16*N bytes,
+but the interpretation of 32 bytes -> 16*N bytes depends on
+whether N==1 or N>1.
+
+Since the second subreg makes sense individually, simplify_subreg
+should bail out rather than ICE on it.  simplify_gen_subreg will
+then do the same (because it already checks validate_subreg).
+This leaves simplify_gen_subreg returning null, requiring the
+caller to take appropriate action.
+
+I think this is relatively likely to occur elsewhere, so the patch
+adds a helper for forcing a subreg, allowing a temporary pseudo to
+be created where necessary.
+
+I'll follow up by using force_subreg in more places.  This patch
+is intended to be a minimal backportable fix for the PR.
+
+gcc/
+	PR target/115464
+	* simplify-rtx.cc (simplify_context::simplify_subreg): Don't try
+	to fold two subregs together if their relationship isn't known
+	at compile time.
+	* explow.h (force_subreg): Declare.
+	* explow.cc (force_subreg): New function.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Use it instead of simplify_gen_subreg.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464.c: New test.
+
+(cherry picked from commit 0970ff46ba6330fc80e8736fc05b2eaeeae0b6a0)
+---
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc   |  2 +-
+ gcc/explow.cc                                     | 15 +++++++++++++++
+ gcc/explow.h                                      |  2 ++
+ gcc/simplify-rtx.cc                               |  5 +++++
+ .../aarch64/sve/acle/general/pr115464.c           | 13 +++++++++++++
+ 5 files changed, 36 insertions(+), 1 deletion(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 0d2edf3f19e..c9182594bc1 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1174,7 +1174,7 @@ public:
+        Advanced SIMD argument as an SVE vector.  */
+     if (!BYTES_BIG_ENDIAN
+ 	&& is_undef (CALL_EXPR_ARG (e.call_expr, 0)))
+-      return simplify_gen_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
++      return force_subreg (mode, e.args[1], GET_MODE (e.args[1]), 0);
+ 
+     rtx_vector_builder builder (VNx16BImode, 16, 2);
+     for (unsigned int i = 0; i < 16; i++)
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index 8e5f6b8e680..f6843398c4b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -745,6 +745,21 @@ force_reg (machine_mode mode, rtx x)
+   return temp;
+ }
+ 
++/* Like simplify_gen_subreg, but force OP into a new register if the
++   subreg cannot be formed directly.  */
++
++rtx
++force_subreg (machine_mode outermode, rtx op,
++	      machine_mode innermode, poly_uint64 byte)
++{
++  rtx x = simplify_gen_subreg (outermode, op, innermode, byte);
++  if (x)
++    return x;
++
++  op = copy_to_mode_reg (innermode, op);
++  return simplify_gen_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index 16aa02cfb68..cbd1fcb7eb3 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -42,6 +42,8 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+    Args are mode (in case value is a constant) and the value.  */
+ extern rtx force_reg (machine_mode, rtx);
+ 
++extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+ 
+diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
+index dceaa13333c..729d408aa55 100644
+--- a/gcc/simplify-rtx.cc
++++ b/gcc/simplify-rtx.cc
+@@ -7612,6 +7612,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op,
+       poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
+       rtx newx;
+ 
++      /* Make sure that the relationship between the two subregs is
++	 known at compile time.  */
++      if (!ordered_p (outersize, innermostsize))
++	return NULL_RTX;
++
+       if (outermode == innermostmode
+ 	  && known_eq (byte, 0U)
+ 	  && known_eq (SUBREG_BYTE (op), 0))
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+new file mode 100644
+index 00000000000..d728d1325ed
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl)
++{
++    return svset_neonq_u16 (svundef_u16 (), permute_tbl.val[1]);
++}
++
++/* { dg-final { scan-assembler {\tmov\tz0\.d, z1\.d\n} } } */
+-- 
+2.46.0
+
+
+From 7edecb21012d88902c60d38f5865bc254eaa9c55 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:30 +0100
+Subject: [PATCH 2/4] aarch64: Use force_subreg in more places
+
+This patch makes the aarch64 code use force_subreg instead of
+simplify_gen_subreg in more places.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+(3) The offset wasn't a simple lowpart or highpart calculation;
+    a later patch will deal with those.
+
+gcc/
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
+	Use force_subreg instead of simplify_gen_subreg.
+	* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svget_impl::expand): Likewise.
+	(svget_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-functions.h
+	(multireg_permute::expand): Likewise.
+
+(cherry picked from commit 1474a8eead4ab390e59ee014befa8c40346679f4)
+---
+ gcc/config/aarch64/aarch64-builtins.cc              | 4 ++--
+ gcc/config/aarch64/aarch64-simd.md                  | 4 ++--
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc     | 8 +++-----
+ gcc/config/aarch64/aarch64-sve-builtins-functions.h | 6 +++---
+ 4 files changed, 10 insertions(+), 12 deletions(-)
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index 75d21de1401..b2e46a073a8 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2510,12 +2510,12 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+       rtx temp2 = gen_reg_rtx (DImode);
+       temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+ 				   subreg_lowpart_offset (d->mode, quadmode));
+-      temp1 = simplify_gen_subreg (V2DImode, temp1, d->mode, 0);
++      temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+       else
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const1_rtx));
+-      op2 = simplify_gen_subreg (d->mode, temp2, GET_MODE (temp2), 0);
++      op2 = force_subreg (d->mode, temp2, GET_MODE (temp2), 0);
+ 
+       /* And recalculate the index.  */
+       lane -= nunits / 4;
+diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
+index 33ab0741e87..5b9efe0b165 100644
+--- a/gcc/config/aarch64/aarch64-simd.md
++++ b/gcc/config/aarch64/aarch64-simd.md
+@@ -412,8 +412,8 @@
+   "TARGET_SIMD"
+   {
+      emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
+-     rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
+-					     <MODE>mode, 0);
++     rtx op0_castsi2qi = force_subreg (<VS:VSI2QI>mode, operands[0],
++				       <MODE>mode, 0);
+      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));
+      emit_insn (gen_clz<mode>2 (operands[0], operands[0]));
+      DONE;
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index c9182594bc1..2c95da79572 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1121,9 +1121,8 @@ public:
+   expand (function_expander &e) const override
+   {
+     /* Fold the access into a subreg rvalue.  */
+-    return simplify_gen_subreg (e.vector_mode (0), e.args[0],
+-				GET_MODE (e.args[0]),
+-				INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
++    return force_subreg (e.vector_mode (0), e.args[0], GET_MODE (e.args[0]),
++			 INTVAL (e.args[1]) * BYTES_PER_SVE_VECTOR);
+   }
+ };
+ 
+@@ -1157,8 +1156,7 @@ public:
+ 	e.add_fixed_operand (indices);
+ 	return e.generate_insn (icode);
+       }
+-    return simplify_gen_subreg (e.result_mode (), e.args[0],
+-				GET_MODE (e.args[0]), 0);
++    return force_subreg (e.result_mode (), e.args[0], GET_MODE (e.args[0]), 0);
+   }
+ };
+ 
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+index 3b8e575e98e..7d06a57ff83 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
++++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+@@ -639,9 +639,9 @@ public:
+       {
+ 	machine_mode elt_mode = e.vector_mode (0);
+ 	rtx arg = e.args[0];
+-	e.args[0] = simplify_gen_subreg (elt_mode, arg, GET_MODE (arg), 0);
+-	e.args.safe_push (simplify_gen_subreg (elt_mode, arg, GET_MODE (arg),
+-					       GET_MODE_SIZE (elt_mode)));
++	e.args[0] = force_subreg (elt_mode, arg, GET_MODE (arg), 0);
++	e.args.safe_push (force_subreg (elt_mode, arg, GET_MODE (arg),
++					GET_MODE_SIZE (elt_mode)));
+       }
+     return e.use_exact_insn (icode);
+   }
+-- 
+2.46.0
+
+
+From 0ab664f41762803a72e5e99025b0512cad493985 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 3/4] aarch64: Add some uses of force_lowpart_subreg
+
+This patch makes more use of force_lowpart_subreg, similarly
+to the recent patch for force_subreg.  The criteria were:
+
+(1) The code is obviously specific to expand (where new pseudos
+    can be created).
+
+(2) The value is obviously an rvalue rather than an lvalue.
+
+gcc/
+	PR target/115464
+	* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
+	(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
+	simplify_gen_subreg and lowpart_subreg.
+	* config/aarch64/aarch64-sve-builtins-base.cc
+	(svset_neonq_impl::expand): Likewise.
+	* config/aarch64/aarch64-sve-builtins-sme.cc
+	(add_load_store_slice_operand): Likewise.
+	* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
+	(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.
+
+gcc/testsuite/
+	PR target/115464
+	* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
+
+(cherry picked from commit 6bd4fbae45d11795a9a6f54b866308d4d7134def)
+---
+ gcc/config/aarch64/aarch64-builtins.cc             | 11 +++++------
+ gcc/config/aarch64/aarch64-sve-builtins-base.cc    |  2 +-
+ gcc/config/aarch64/aarch64-sve-builtins-sme.cc     |  2 +-
+ gcc/config/aarch64/aarch64.cc                      | 14 +++++---------
+ .../aarch64/sve/acle/general/pr115464_2.c          | 11 +++++++++++
+ 5 files changed, 23 insertions(+), 17 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+
+diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
+index b2e46a073a8..264b9560709 100644
+--- a/gcc/config/aarch64/aarch64-builtins.cc
++++ b/gcc/config/aarch64/aarch64-builtins.cc
+@@ -2497,8 +2497,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+   int lane = INTVAL (lane_idx);
+ 
+   if (lane < nunits / 4)
+-    op2 = simplify_gen_subreg (d->mode, op2, quadmode,
+-			       subreg_lowpart_offset (d->mode, quadmode));
++    op2 = force_lowpart_subreg (d->mode, op2, quadmode);
+   else
+     {
+       /* Select the upper 64 bits, either a V2SF or V4HF, this however
+@@ -2508,8 +2507,7 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
+ 	 gen_highpart_mode generates code that isn't optimal.  */
+       rtx temp1 = gen_reg_rtx (d->mode);
+       rtx temp2 = gen_reg_rtx (DImode);
+-      temp1 = simplify_gen_subreg (d->mode, op2, quadmode,
+-				   subreg_lowpart_offset (d->mode, quadmode));
++      temp1 = force_lowpart_subreg (d->mode, op2, quadmode);
+       temp1 = force_subreg (V2DImode, temp1, d->mode, 0);
+       if (BYTES_BIG_ENDIAN)
+ 	emit_insn (gen_aarch64_get_lanev2di (temp2, temp1, const0_rtx));
+@@ -2754,7 +2752,7 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+ 	case AARCH64_WSR64:
+ 	case AARCH64_WSRF64:
+ 	case AARCH64_WSR128:
+-	  subreg = lowpart_subreg (sysreg_mode, input_val, mode);
++	  subreg = force_lowpart_subreg (sysreg_mode, input_val, mode);
+ 	  break;
+ 	case AARCH64_WSRF:
+ 	  subreg = gen_lowpart_SUBREG (SImode, input_val);
+@@ -2789,7 +2787,8 @@ aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode)
+     case AARCH64_RSR64:
+     case AARCH64_RSRF64:
+     case AARCH64_RSR128:
+-      return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, sysreg_mode);
++      return force_lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)),
++				   target, sysreg_mode);
+     case AARCH64_RSRF:
+       subreg = gen_lowpart_SUBREG (SImode, target);
+       return gen_lowpart_SUBREG (SFmode, subreg);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+index 2c95da79572..3c970e9c5f8 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+@@ -1183,7 +1183,7 @@ public:
+     if (BYTES_BIG_ENDIAN)
+       return e.use_exact_insn (code_for_aarch64_sve_set_neonq (mode));
+     insn_code icode = code_for_vcond_mask (mode, mode);
+-    e.args[1] = lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
++    e.args[1] = force_lowpart_subreg (mode, e.args[1], GET_MODE (e.args[1]));
+     e.add_output_operand (icode);
+     e.add_input_operand (icode, e.args[1]);
+     e.add_input_operand (icode, e.args[0]);
+diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+index f4c91bcbb95..b66b35ae60b 100644
+--- a/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
++++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.cc
+@@ -112,7 +112,7 @@ add_load_store_slice_operand (function_expander &e, insn_code icode,
+   rtx base = e.args[argno];
+   if (e.mode_suffix_id == MODE_vnum)
+     {
+-      rtx vnum = lowpart_subreg (SImode, e.args[vnum_argno], DImode);
++      rtx vnum = force_lowpart_subreg (SImode, e.args[vnum_argno], DImode);
+       base = simplify_gen_binary (PLUS, SImode, base, vnum);
+     }
+   e.add_input_operand (icode, base);
+diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
+index 1beec94629d..a064aeecbc0 100644
+--- a/gcc/config/aarch64/aarch64.cc
++++ b/gcc/config/aarch64/aarch64.cc
+@@ -3284,7 +3284,7 @@ aarch64_sve_reinterpret (machine_mode mode, rtx x)
+   /* can_change_mode_class must only return true if subregs and svreinterprets
+      have the same semantics.  */
+   if (targetm.can_change_mode_class (GET_MODE (x), mode, FP_REGS))
+-    return lowpart_subreg (mode, x, GET_MODE (x));
++    return force_lowpart_subreg (mode, x, GET_MODE (x));
+ 
+   rtx res = gen_reg_rtx (mode);
+   x = force_reg (GET_MODE (x), x);
+@@ -26979,9 +26979,8 @@ aarch64_addti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			    rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = gen_lowpart (DImode, op1);
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+   *high_in1 = gen_highpart (DImode, op1);
+   *high_in2 = simplify_gen_subreg (DImode, op2, TImode,
+@@ -27013,11 +27012,8 @@ aarch64_subvti_scratch_regs (rtx op1, rtx op2, rtx *low_dest,
+ 			     rtx *high_in2)
+ {
+   *low_dest = gen_reg_rtx (DImode);
+-  *low_in1 = simplify_gen_subreg (DImode, op1, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
+-
+-  *low_in2 = simplify_gen_subreg (DImode, op2, TImode,
+-				  subreg_lowpart_offset (DImode, TImode));
++  *low_in1 = force_lowpart_subreg (DImode, op1, TImode);
++  *low_in2 = force_lowpart_subreg (DImode, op2, TImode);
+   *high_dest = gen_reg_rtx (DImode);
+ 
+   *high_in1 = simplify_gen_subreg (DImode, op1, TImode,
+diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+new file mode 100644
+index 00000000000..f561c34f732
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr115464_2.c
+@@ -0,0 +1,11 @@
++/* { dg-options "-O2" } */
++
++#include <arm_neon.h>
++#include <arm_sve.h>
++#include <arm_neon_sve_bridge.h>
++
++svuint16_t
++convolve4_4_x (uint16x8x2_t permute_tbl, svuint16_t a)
++{
++    return svset_neonq_u16 (a, permute_tbl.val[1]);
++}
+-- 
+2.46.0
+
+
+From e21a377dea6edfaaa494f07974135e58ff66eef1 Mon Sep 17 00:00:00 2001
+From: Richard Sandiford <richard.sandiford@arm.com>
+Date: Tue, 18 Jun 2024 12:22:31 +0100
+Subject: [PATCH 4/4] Add force_lowpart_subreg
+
+optabs had a local function called lowpart_subreg_maybe_copy
+that is very similar to the lowpart version of force_subreg.
+This patch adds a force_lowpart_subreg wrapper around
+force_subreg and uses it in optabs.cc.
+
+The only difference between the old and new functions is that
+the old one asserted success while the new one doesn't.
+It's common not to assert elsewhere when taking subregs;
+normally a null result is enough.
+
+Later patches will make more use of the new function.
+
+gcc/
+	* explow.h (force_lowpart_subreg): Declare.
+	* explow.cc (force_lowpart_subreg): New function.
+	* optabs.cc (lowpart_subreg_maybe_copy): Delete.
+	(expand_absneg_bit): Use force_lowpart_subreg instead of
+	lowpart_subreg_maybe_copy.
+	(expand_copysign_bit): Likewise.
+
+(cherry picked from commit 5f40d1c0cc6ce91ef28d326b8707b3f05e6f239c)
+---
+ gcc/explow.cc | 14 ++++++++++++++
+ gcc/explow.h  |  1 +
+ gcc/optabs.cc | 24 ++----------------------
+ 3 files changed, 17 insertions(+), 22 deletions(-)
+
+diff --git a/gcc/explow.cc b/gcc/explow.cc
+index f6843398c4b..5fdfa81f69b 100644
+--- a/gcc/explow.cc
++++ b/gcc/explow.cc
+@@ -760,6 +760,20 @@ force_subreg (machine_mode outermode, rtx op,
+   return simplify_gen_subreg (outermode, op, innermode, byte);
+ }
+ 
++/* Try to return an rvalue expression for the OUTERMODE lowpart of OP,
++   which has mode INNERMODE.  Allow OP to be forced into a new register
++   if necessary.
++
++   Return null on failure.  */
++
++rtx
++force_lowpart_subreg (machine_mode outermode, rtx op,
++		      machine_mode innermode)
++{
++  auto byte = subreg_lowpart_offset (outermode, innermode);
++  return force_subreg (outermode, op, innermode, byte);
++}
++
+ /* If X is a memory ref, copy its contents to a new temp reg and return
+    that reg.  Otherwise, return X.  */
+ 
+diff --git a/gcc/explow.h b/gcc/explow.h
+index cbd1fcb7eb3..dd654649b06 100644
+--- a/gcc/explow.h
++++ b/gcc/explow.h
+@@ -43,6 +43,7 @@ extern rtx copy_to_suggested_reg (rtx, rtx, machine_mode);
+ extern rtx force_reg (machine_mode, rtx);
+ 
+ extern rtx force_subreg (machine_mode, rtx, machine_mode, poly_uint64);
++extern rtx force_lowpart_subreg (machine_mode, rtx, machine_mode);
+ 
+ /* Return given rtx, copied into a new temp reg if it was in memory.  */
+ extern rtx force_not_mem (rtx);
+diff --git a/gcc/optabs.cc b/gcc/optabs.cc
+index ce91f94ed43..804c0dc73ba 100644
+--- a/gcc/optabs.cc
++++ b/gcc/optabs.cc
+@@ -3096,26 +3096,6 @@ expand_ffs (scalar_int_mode mode, rtx op0, rtx target)
+   return 0;
+ }
+ 
+-/* Extract the OMODE lowpart from VAL, which has IMODE.  Under certain
+-   conditions, VAL may already be a SUBREG against which we cannot generate
+-   a further SUBREG.  In this case, we expect forcing the value into a
+-   register will work around the situation.  */
+-
+-static rtx
+-lowpart_subreg_maybe_copy (machine_mode omode, rtx val,
+-			   machine_mode imode)
+-{
+-  rtx ret;
+-  ret = lowpart_subreg (omode, val, imode);
+-  if (ret == NULL)
+-    {
+-      val = force_reg (imode, val);
+-      ret = lowpart_subreg (omode, val, imode);
+-      gcc_assert (ret != NULL);
+-    }
+-  return ret;
+-}
+-
+ /* Expand a floating point absolute value or negation operation via a
+    logical operation on the sign bit.  */
+ 
+@@ -3204,7 +3184,7 @@ expand_absneg_bit (enum rtx_code code, scalar_float_mode mode,
+ 			   gen_lowpart (imode, op0),
+ 			   immed_wide_int_const (mask, imode),
+ 		           gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+ 
+       set_dst_reg_note (get_last_insn (), REG_EQUAL,
+ 			gen_rtx_fmt_e (code, mode, copy_rtx (op0)),
+@@ -4043,7 +4023,7 @@ expand_copysign_bit (scalar_float_mode mode, rtx op0, rtx op1, rtx target,
+ 
+       temp = expand_binop (imode, ior_optab, op0, op1,
+ 			   gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN);
+-      target = lowpart_subreg_maybe_copy (mode, temp, imode);
++      target = force_lowpart_subreg (mode, temp, imode);
+     }
+ 
+   return target;
+-- 
+2.46.0
+

cross/grub-efi-x86/APKBUILD

@@ -3,7 +3,7 @@
 
 pkgname=grub-efi-x86
 pkgver=2.12
-pkgrel=5
+pkgrel=6
 
 _arch="x86"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -22,5 +22,5 @@ package() {
 }
 
 sha512sums="
-3cc14376ad5dc2a4d8488d49199d1257c5024c8c4afcbcdf67a0cd7a66e75962191850cca4248ce13abf060b4d9e2fd0966ef6adeb38a00d58c9e4054eec1e9d  grub-efi-2.12-r5-x86-edge.apk
+bad54187b4fbb9f78f2d619ff9a652a4927c557070c2c39334fd9900ae5aeb956144055602ca56295d7966c2d10090ef142a073dd67eb14f7b41ba0d54c78d4d  grub-efi-2.12-r6-x86-edge.apk
 "

cross/musl-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-aarch64
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-aarch64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-5ad546aca584d77f6fcf7d92bc5e6432d8c32b3db2922a4099423649e674b5c149464bd0048021e50b18398a00382bbeb6a0a598148bea4fa6d783f5c4c4445d  musl-1.2.5-r1-aarch64-edge.apk
-b6fed1441c0eacfea0061967915a876ce0af79b83511d9b05ae7e7cf489d88e36a544fa7f7512f390429d7d0217b672c04a83dfceea603ce0e86d2a47c50f4cc  musl-dev-1.2.5-r1-aarch64-edge.apk
+a3c660153e2cd1859a83e692c4d1c9f92bb442948ec4ed63412ac1d75502fa40a5a383bb548c8ac98d83fdd27f067304e876be1e15f41eaa09f1414cf5d4e189  musl-1.2.5-r2-aarch64-edge.apk
+6e921c1a761125e768e78e072585b226180c1447f04a4d5fc50564787b30f9c1520b3bfe90d835cfba1716fc4672d3df95a0883187adb50627eed9a3c4249a04  musl-dev-1.2.5-r2-aarch64-edge.apk
 "

cross/musl-armhf/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-armhf
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-armhf:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-148883dfd80bb670df4c6a919aaf3334d203a87fac98df8046a920a2e4c1c3439347f5653abc2994e9a9fe2946764395cd83e2f2437ab903e37f8ad3fcc6637a  musl-1.2.5-r1-armhf-edge.apk
-052f4f3ff6974aadbe90c1a69c4b29a1fefc25d2f2f794b3d55ed49b79a94dab900592a65b3c80ae9824580eab4fb99cb2cfdf9399354e74a1804871d97774a0  musl-dev-1.2.5-r1-armhf-edge.apk
+20f07f25e5267acac97f7f7bf98763869c9a193bf44d1ef2b79f46f2e854aeabe2baa74d0311057541fb99179addbd43c08c56d1361ed349ae22973141f639c5  musl-1.2.5-r2-armhf-edge.apk
+4afb4520885704849bec649f5488add0a3a7b25005172d69f03337cf5b0a82d9f564cba11bbfa84a43a9386e027a8516fcc4573210b4e1fe340cc295a7f52499  musl-dev-1.2.5-r2-armhf-edge.apk
 "

cross/musl-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-armv7
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-armv7:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-f3da7602184940c3ca4ddc973fd127fe08eb5e9141cf4c22cf49ccf131ef836b7f697f20dc64c7e18661f88779354c8b93c14521d18fb2e83d10638c3c8ed7d5  musl-1.2.5-r1-armv7-edge.apk
-b2678887dfc565691d92c1604137d984c5ce68f7c39c1ec2fd7200d4df4f818d4690c323f93b76ca1d4498a5dc36dff61959e06cc749099c706f85601d915d8e  musl-dev-1.2.5-r1-armv7-edge.apk
+0a542c678cfc7ed0cc4246985bd1ecce63247ca4db0ea9fde7c1ee2b30f683b46d7c4011b21931d19fc7c3faeb787413d243580417ec90f745b77534277a6f68  musl-1.2.5-r2-armv7-edge.apk
+26516f5ffc1f04223cce8bae2122a2eab17ec59ce1ef0c1d2382394d9dd0e014ac77336639592f24d15f0ec5120ea7b8329febab1bbbaf3dfecb777b944d6337  musl-dev-1.2.5-r2-armv7-edge.apk
 "

cross/musl-riscv64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-riscv64
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-riscv64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-822f24faaf2285174742788da0dceef3bada4dbd0db9f67362876b3c0ab6bc647a0f2f0cc70e2e28dbb90121f08b65640a344e7cae8416a84bfb389db32e7d9c  musl-1.2.5-r1-riscv64-edge.apk
-04ac4a81d713f71b68082767ce2afab3ce458730664c140f49a0b33f257666a6b4289c5b53935fe16345f8445a458e5307511773651c4574526cfaaf232c239a  musl-dev-1.2.5-r1-riscv64-edge.apk
+ebc1f6759f73c492c00429fd735bd1f3f67bb5a1530156f0c0a821f693b415ba7b8807c22134ce8bd4043f18b12356151c4bfaff59946d059cd0523ebc8aad57  musl-1.2.5-r2-riscv64-edge.apk
+d5209392baedcee71455faa51f6a2e60a90b2bc51c1f5f2c9fb03ff6692b246225d8db7dd5f9165d76bd9d2463e797c9b3c805e04887a4b4b90ec55e96ced627  musl-dev-1.2.5-r2-riscv64-edge.apk
 "

cross/musl-x86/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-x86
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="x86_64"
 subpackages="musl-dev-x86:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-53a30a57f0db29e8d73d7190590fce18a19bcd358f9b0f3d4fa0b8821dad4ed5f1065c3c07dbc373a23cbd98c9a9dc1c2c2d864ac88eefd53dc5f89d8e57ed67  musl-1.2.5-r1-x86-edge.apk
-e9178fcfe27bdc7568c35889cff8cf20829f67460fd6dc22a6ca0465063a809081ee1267b4275432d23d1e7d457a4b207a0ff11c678233c4e430a1173d4ccea8  musl-dev-1.2.5-r1-x86-edge.apk
+bde9b17b3f8b696dd863509713113b720bdff8d125e98eed5165f5fa0934d3a8adc317ffb319e3c045b99389ebb0ac08896c0bedd6d0e7461c9f2d98ffee62f9  musl-1.2.5-r2-x86-edge.apk
+cfd0b502e1237024736b6215ac944299664f4b44802533f5cf6b5239a15c22bdc7782004e1485e15d8184ca0cc9afbf704c12cc39d4fe93611f65c8915d595a7  musl-dev-1.2.5-r2-x86-edge.apk
 "

cross/musl-x86_64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-x86_64
 pkgver=1.2.5
-pkgrel=1
+pkgrel=2
 arch="aarch64"
 subpackages="musl-dev-x86_64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-5506970c66b6da294d32961e94cadc6926a7405915a3d4dd519ed8c2aae829f2fbfaab2ccc8d0794f4aa102aa3e8cbd62099aa54668a11ac0c5072f59befece6  musl-1.2.5-r1-x86_64-edge.apk
-bd2602e59831ba860a548c8281bb62be3382b4035f18c9e36350be644db61a762a413e1d696697d402a57d4bc565faf86c2a212e27c9b9a890d765f794bbe829  musl-dev-1.2.5-r1-x86_64-edge.apk
+2554e2ac0b3f02904197de5317db836e5dbd2631d2ab6e59c3453eeff9b1647b9110005cfe7922470512e7d8b561c94769bf348f7f959754fdb1ca05b403d99b  musl-1.2.5-r2-x86_64-edge.apk
+9a29dcb8cd82da7eb929269c75d2c6637a0ce457526c4960164bcff424f6a0cf581b5a4b2f0020624360d1e5c71b10042dbe59db21df4cd6ffa14b0845c71802  musl-dev-1.2.5-r2-x86_64-edge.apk
 "

device/archived/device-samsung-coreprimevelte-downstream/APKBUILD

@@ -4,14 +4,14 @@
 pkgname=device-samsung-coreprimevelte-downstream
 pkgdesc="Samsung Galaxy Core Prime VE LTE downstream"
 pkgver=1
-pkgrel=0
+pkgrel=3
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
 options="!check !archcheck"
-depends="mkbootimg linux-samsung-coreprimevelte-downstream postmarketos-base pxa-mkbootimg u-boot-tools"
+depends="mkbootimg linux-samsung-coreprimevelte-downstream postmarketos-base postmarketos-initramfs-minimal pxa-mkbootimg u-boot-tools"
 makedepends="devicepkg-dev"
-subpackages="$pkgname-nonfree-firmware:nonfree_firmware"
+_pmb_recommends="firmware-samsung-pxa1908-downstream"
 source="deviceinfo 90-coreprimevelte.conf"
 
 build() {
@@ -23,12 +23,6 @@ package() {
 	install -Dm444 $startdir/90-coreprimevelte.conf $pkgdir/etc/sysctl.d/90-coreprimevelte.conf
 }
 
-nonfree_firmware() {
-	pkgdesc="Wi-Fi firmware"
-	depends="firmware-samsung-pxa1908"
-	mkdir "$subpkgdir"
-}
-
 sha512sums="
 741f46736c2742d4a6f118a924eee89954fb14e5b1dc00f372bda41b63ec975cf960909f915fcb31ad965f136a712905bc8626cd7e530f40e110885f7c861790  deviceinfo
 4854cc57b86e1199dbc165110514e672dabf45044fe9f7ebbde5b2b24768fb5497273b5f38612cf2dfeffc9bf0648c725114b4fa01165bf7fb02f7d741ee5806  90-coreprimevelte.conf

device/archived/device-shift-axolotl-downstream/APKBUILD

@@ -4,7 +4,7 @@
 pkgname=device-shift-axolotl-downstream
 pkgdesc="SHIFT6mq downstream"
 pkgver=1
-pkgrel=1
+pkgrel=2
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -27,5 +27,5 @@ package() {
 }
 
 sha512sums="
-3a60faa3024b6a066e5f5319c0e651ffe4980be51cc1b848a946b96cd861be16d651dc2184993eca89f28fe442a39a1a78f67753dc1bb295cab4bdaaa6f2fe49  deviceinfo
+75bc9e4b1225f3988bef27763d5961160e3dbdb25260327c0390290827b8e946a27ed7f8b0a810f89d696112ca9d220652c8789cbc86f898d2292dd0ae2f61e4  deviceinfo
 "

device/archived/device-shift-axolotl-downstream/deviceinfo

@@ -18,7 +18,7 @@ deviceinfo_screen_height="2160"
 
 # Bootloader related
 deviceinfo_flash_method="fastboot"
-deviceinfo_kernel_cmdline="console=ttyMSM0,115200n8 buildvariant=userdebug androidboot.hardware=qcom user_debug=31 msm_rtb.filter=0x37 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 sched_enable_hmp=1 sched_enable_power_aware=1 service_locator.enable=1 swiotlb=2048 androidboot.usbconfigfs=true androidboot.usbcontroller=a800000.dwc3 firmware_class.path=/vendor/firmware_mnt/image loop.max_part=7 ramoops.mem_address=0xac000000 ramoops.mem_size=0x200000 ramoops.console_size=0x40000 PMOS_NO_OUTPUT_REDIRECT"
+deviceinfo_kernel_cmdline="console=ttyMSM0,115200n8 buildvariant=userdebug androidboot.hardware=qcom user_debug=31 msm_rtb.filter=0x37 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 sched_enable_hmp=1 sched_enable_power_aware=1 service_locator.enable=1 swiotlb=2048 androidboot.usbconfigfs=true androidboot.usbcontroller=a800000.dwc3 firmware_class.path=/vendor/firmware_mnt/image loop.max_part=7 ramoops.mem_address=0xac000000 ramoops.mem_size=0x200000 ramoops.console_size=0x40000"
 deviceinfo_generate_bootimg="true"
 deviceinfo_bootimg_qcdt="false"
 deviceinfo_bootimg_dtb_second="false"

device/community/device-arrow-db410c/APKBUILD

@@ -3,7 +3,7 @@
 pkgname=device-arrow-db410c
 pkgdesc="Arrow DragonBoard 410c"
 pkgver=4
-pkgrel=0
+pkgrel=1
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -32,6 +32,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-9e4e3c89c6328c60a3e6a02bae30e79863a512760be04177c710827788970963be3679602e288ddee1a4a054e0e80d707ad53d15db6918998680119882e3eab8  deviceinfo
+b7431dcf918509458637442814d6f91f1532c75cd483be65d14dedd7af81f2f565187a190b3e3537474d00eec71cdb4ef6eb7fe3246ecde5a6c7b92593e71207  deviceinfo
 ccd6758cb4954eb0a96c7fb15e732e8147414f8edc498d9faf7d04ddef85d817733669ec1a6003e623e8392f3f6bb85f71160efe4e82f27e300d58aa6f5c8549  modules-initfs
 "

device/community/device-arrow-db410c/deviceinfo

@@ -21,7 +21,7 @@ deviceinfo_getty="ttyMSM0;115200"
 
 # Bootloader related
 deviceinfo_flash_method="fastboot"
-deviceinfo_kernel_cmdline="earlycon console=ttyMSM0,115200 PMOS_NO_OUTPUT_REDIRECT"
+deviceinfo_kernel_cmdline="earlycon console=ttyMSM0,115200"
 deviceinfo_generate_bootimg="true"
 deviceinfo_generate_extlinux_config="true"
 deviceinfo_bootimg_dtb_second="true"

device/community/device-bq-paella/APKBUILD

@@ -3,7 +3,7 @@
 pkgname=device-bq-paella
 pkgdesc="BQ Aquaris X5"
 pkgver=8
-pkgrel=0
+pkgrel=1
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -38,6 +38,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-ae1d413f189856d5f9ccc6a3a64e6cd719ad3cf7e4d1f5b358201037f7fcad2098a33eedfb83278ecf80073bdfbfd49cc796b43da4992f7b2bd3a6dbaa266c40  deviceinfo
+75e857f36f627d1ef209bfc79bac574b432ecb93a0e0de131675de43c43cef15e455284bab7b635376d21fd908e8cd21e6e918c6bd03c6e711179489f56e39a5  deviceinfo
 ebf6a40372329116a25df1407e671365bb2bf0613f61f0a572fc77890fb0a1760259ab35ed9f002ef2a5c6ee8836bc7bbeb50bf5ac3de14c11e6d96872ad3644  modules-initfs
 "

device/community/device-bq-paella/deviceinfo

@@ -21,7 +21,7 @@ deviceinfo_getty="ttyMSM0;115200"
 
 # Bootloader related
 deviceinfo_flash_method="fastboot"
-deviceinfo_kernel_cmdline="earlycon console=ttyMSM0,115200 PMOS_NO_OUTPUT_REDIRECT"
+deviceinfo_kernel_cmdline="earlycon console=ttyMSM0,115200"
 deviceinfo_generate_bootimg="true"
 deviceinfo_generate_extlinux_config="true"
 deviceinfo_flash_offset_base="0x80000000"

device/community/device-fairphone-fp4/81-libssc-fairphone-fp4.rules

@@ -0,0 +1,3 @@
+# iio-sensor-proxy with libssc: accelerometer mount matrix
+
+SUBSYSTEM=="misc", KERNEL=="fastrpc-*", ENV{ACCEL_MOUNT_MATRIX}+="-1, 0, 0; 0, -1, 0; 0, 0, -1"

device/community/device-fairphone-fp4/APKBUILD

@@ -1,34 +1,52 @@
 # Reference: <https://postmarketos.org/devicepkg>
-# Maintainer: Luca Weiss <luca@z3ntu.xyz>
+# Maintainer: Luca Weiss <luca@lucaweiss.eu>
 pkgname=device-fairphone-fp4
 pkgdesc="Fairphone 4"
-pkgver=2
-pkgrel=3
+pkgver=3
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
 options="!check !archcheck"
 depends="
 	bootmac
+	firmware-fairphone-fp4-adreno
+	firmware-fairphone-fp4-adsp
+	firmware-fairphone-fp4-bluetooth
+	firmware-fairphone-fp4-cdsp
+	firmware-fairphone-fp4-hexagonfs
+	firmware-fairphone-fp4-ipa
+	firmware-fairphone-fp4-modem
+	firmware-fairphone-fp4-wlan
+	firmware-qcom-adreno-a630
+	hexagonrpcd
+	hexagonrpcd-openrc
+	linux-firmware-ath10k
 	linux-postmarketos-qcom-sm6350
 	make-dynpart-mappings
 	mesa-vulkan-freedreno
 	mkbootimg
+	msm-modem
+	msm-modem-uim-selection
+	pd-mapper
+	pd-mapper-openrc
 	postmarketos-base
 	qbootctl
 	qbootctl-openrc
 	swclock-offset
+	tqftpserv
+	tqftpserv-openrc
 "
 makedepends="devicepkg-dev"
+replaces="hexagonrpcd-openrc"
 install="$pkgname.post-install $pkgname.post-upgrade"
 source="
+	81-libssc-fairphone-fp4.rules
 	90-feedbackd-aw8695.rules
 	deviceinfo
+	hexagonrpcd.confd
 	modules-initfs
 	"
-subpackages="
-	$pkgname-nonfree-firmware:nonfree_firmware
-"
 
 build() {
 	devicepkg_build $startdir $pkgname
@@ -37,33 +55,18 @@ build() {
 package() {
 	devicepkg_package $startdir $pkgname
 
+	install -Dm644 "$srcdir"/81-libssc-fairphone-fp4.rules \
+		"$pkgdir"/usr/lib/udev/rules.d/81-libssc-fairphone-fp4.rules
 	install -Dm644 "$srcdir"/90-feedbackd-aw8695.rules \
 		"$pkgdir"/usr/lib/udev/rules.d/90-feedbackd-aw8695.rules
-}
-
-nonfree_firmware() {
-	pkgdesc="Firmware for Modem, WiFi, etc."
-	depends="
-		firmware-fairphone-fp4-adreno
-		firmware-fairphone-fp4-adsp
-		firmware-fairphone-fp4-bluetooth
-		firmware-fairphone-fp4-cdsp
-		firmware-fairphone-fp4-ipa
-		firmware-fairphone-fp4-modem
-		firmware-fairphone-fp4-wlan
-		firmware-qcom-adreno-a630
-		linux-firmware-ath10k
-		msm-modem
-		msm-modem-uim-selection
-		pd-mapper
-		tqftpserv
-		"
-	install="$subpkgname.post-install"
-	mkdir "$subpkgdir"
+	install -Dm644 "$srcdir"/hexagonrpcd.confd \
+		"$pkgdir"/etc/conf.d/hexagonrpcd-adsp-sensorspd
 }
 
 sha512sums="
+2c16ba75e0077b2b1eaefa4c73b287475505a1aeb291ec29316d41cc094277320f9d2aaabfd91eb1dc0f488ab2d61a94faef16e7afe0f1e226779113761b9a37  81-libssc-fairphone-fp4.rules
 2974ccc172bf1299daeb0bc746879b3a1db1fbc3a2b163a02a6554fed6ed9f733144bcf976cd2441c5664d496dcce3ae943f4314c653470dc07dda0de5ad632b  90-feedbackd-aw8695.rules
-e223df827d1d18507197d64fc409f527514f7f76b68f784811b7b59452260dbd72133c85277b1e7df38b0058e0f16ac0d1174104a193b7f6c8dcf64577863eba  deviceinfo
+9549f105f865d230e7b67819c96b7e06a5ed4d5808f083099a408934ffbacdb412984b861f6756fa4fde94b51e6a268b8d2ce9fed6f13ee3e8041bb96492310a  deviceinfo
+6a3d620f2cc60308a62ff651ffb00a5ee1f092131cca9d33b6afd61c8a372a3fd7d46540162213593107e0943b33f3f0119d003d43dcd06dbde757390a6c1729  hexagonrpcd.confd
 52bb7ed829caa4dcff9728bd6e3cdf118b3c7ee7dfe90df0d4e6422dd67bf3258ae2a4d2dc7599da4182fbd8eb47a0e1d20c58198dc17f2bf178b8f01a8887f7  modules-initfs
 "

device/community/device-fairphone-fp4/device-fairphone-fp4.post-install

@@ -1,2 +1,5 @@
 #!/bin/sh
+rc-update add hexagonrpcd-adsp-sensorspd default
+rc-update add pd-mapper boot
 rc-update add qbootctl default
+rc-update add tqftpserv boot

device/community/device-fairphone-fp4/deviceinfo

@@ -23,7 +23,7 @@ deviceinfo_getty="ttyMSM0;115200"
 
 # Bootloader related
 deviceinfo_flash_method="fastboot"
-deviceinfo_kernel_cmdline="PMOS_NO_OUTPUT_REDIRECT"
+
 deviceinfo_generate_bootimg="true"
 deviceinfo_bootimg_qcdt="false"
 deviceinfo_bootimg_mtk_mkimage="false"

device/community/device-fairphone-fp4/hexagonrpcd.confd

@@ -0,0 +1,2 @@
+# Fairphone 4 specific hexagonrpcd firmware directory
+hexagonrpcd_fw_dir="/usr/share/qcom/sm7225/Fairphone/fairphone4"

device/community/device-generic-x86_64/APKBUILD

@@ -2,8 +2,8 @@
 # Co-Maintainer: Oliver Smith <ollieparanoid@postmarketos.org>
 pkgname=device-generic-x86_64
 pkgdesc="Generic x86_64 system, with EFI"
-pkgver=13
-pkgrel=1
+pkgver=14
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="x86_64"
@@ -29,6 +29,7 @@ _pmb_recommends="
 	linux-firmware
 	oem-amd
 	oem-intel
+	oem-nvidia
 "
 provides="device-tablet-x64uefi=$pkgver-r$pkgrel device-tablet-x86uefi=$pkgver-r$pkgrel"
 replaces="device-tablet-x64uefi device-tablet-x86uefi"
@@ -59,5 +60,5 @@ kernel_lts() {
 
 sha512sums="
 e9dfcd70ccfb9a0fdaa0cdc52faf3be96d6de8af8c60a758bb703c515b0648cec4552e0eaf56e5168b0004cd3fc4b28118abb05dad2c581d3579a2e9134862cb  deviceinfo
-cf9ad3e80b43aa799a8123289e3ab77f6a1c37cee3d48db737688b93afd4f1094db76008ec0f28358c35dd1e115c4fabf9452f9abee76481a2630f02e3ae0953  modules-initfs
+e464ef0ad4a4c34d2d53f69c4612b612ea878a77c9efdef69b0f842edf701036c8218809fd63aac286d6a08ae07f39e568199fc3e38d145e716c1723e7215019  modules-initfs
 "

device/community/device-generic-x86_64/modules-initfs

@@ -2,6 +2,7 @@ ahci
 ehci_hcd
 ehci_pci
 hid-multitouch
+hid_apple
 hid_generic
 i2c_hid_acpi
 jbd2

device/community/device-google-gru/APKBUILD

@@ -2,8 +2,8 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-gru
 pkgdesc="Google Gru Chromebooks"
-pkgver=5
-pkgrel=7
+pkgver=7
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -53,6 +53,6 @@ nonfree_firmware() {
 
 
 sha512sums="
-bf5d1d687e5dd4231eea758611799bfb2aef8caf3314e9469093bf7158ed85dd3aa2fd7894a1a97542a076ddd2ca8a735e54b012f6bee9522fea85d8556a8b90  deviceinfo
+7815e3a164720b5ad0df7ce8d12b12fe85cc4bb7bf4a09ccc0eb831a58a920026fd92d545f4d6fb459a688e15b9d542e360fd597cd5d3b01a3ea338c3928d2a3  deviceinfo
 a750a0c41068082e0b82351d5aec91715e1a5215b09b26fec644dfe259cea2d662e878433a732a8c06dab2a9b420baec2bcc6161d8357cf3ed770239c5165090  modules-initfs
 "

device/community/device-google-gru/deviceinfo

@@ -16,6 +16,7 @@ deviceinfo_chassis="convertible"
 deviceinfo_keyboard="true"
 deviceinfo_external_storage="true"
 deviceinfo_gpu_accelerated="true"
+deviceinfo_disable_dhcpd="true"
 
 # Bootloader related
 deviceinfo_flash_method="none"
@@ -24,5 +25,6 @@ deviceinfo_cgpt_kpart="/boot/vmlinuz.kpart"
 deviceinfo_cgpt_kpart_start="8192"
 deviceinfo_cgpt_kpart_size="65536"
 deviceinfo_depthcharge_board="gru"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"
 deviceinfo_generate_extlinux_config="true"

device/community/device-google-kukui/APKBUILD

@@ -2,8 +2,8 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-kukui
 pkgdesc="Google Kukui Chromebooks"
-pkgver=6
-pkgrel=6
+pkgver=8
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -73,6 +73,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-4c7f6c37afbf2fbd9169f158dc8ab2c29599a3eb1f945b51c46dfb3a385ee007c3524b8c689dfc19f51f4e850ec87550f7af6ab3c0590ba713ba14f549a3efb2  deviceinfo
+ecd503069ecf272ddc238bd49dc257a1f3e0f4c20b322238e2da83104b94b331c22886d1591b6fe0b78c986e15ac6251e364ec1b750f9125ea722a6b1a79e2b8  deviceinfo
 8e95624610dae7d18684056396c9e82635ddce7303d6770e965f9372ffa101fdfd5f8337bc7368004890e9836798663a98c142c52ed63795877ea37ac8da56af  modules-initfs
 "

device/community/device-google-kukui/deviceinfo

@@ -16,6 +16,7 @@ deviceinfo_chassis="convertible"
 deviceinfo_keyboard="true"
 deviceinfo_external_storage="true"
 deviceinfo_gpu_accelerated="true"
+deviceinfo_disable_dhcpd="true"
 
 # Bootloader related
 deviceinfo_kernel_cmdline="console=null"
@@ -31,4 +32,5 @@ deviceinfo_cgpt_kpart_size="65536"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8183"
 # board here.
 deviceinfo_depthcharge_board="mt8183"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"

device/community/device-google-oak/APKBUILD

@@ -3,8 +3,8 @@
 # Co-Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-oak
 pkgdesc="Google Oak Chromebooks"
-pkgver=4
-pkgrel=6
+pkgver=6
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -15,6 +15,7 @@ depends="
 	linux-postmarketos-mediatek-mt8173
 	postmarketos-base
 	postmarketos-cros-common
+	postmarketos-initramfs-minimal
 "
 makedepends="devicepkg-dev"
 source="deviceinfo modules-initfs"
@@ -39,6 +40,6 @@ nonfree_firmware() {
 }
 
 sha512sums="
-866dad1295698accf952a52bdabd8be99d3449c6131d305067ed404e917a36a5d28e2482c6a205774c9438d17b9d50a2da66a26d58f147ae1aeaa4f225a377c8  deviceinfo
+d082e6c155347f662403f611f44c3eddb2a0548397bec4f29b882f371a18efa9c2628a88599b19c0c58c1886d0c25035367f02651a60fb6c3293faa1449b83d5  deviceinfo
 4b0197eacfeeb4b13f5abc26950f570ee762742547674ce10110ccea63eb46630a2e3b5f87e9c9a1f9deda21baf05bec248ab7a65656687ec94d296b5657dafa  modules-initfs
 "

device/community/device-google-oak/deviceinfo

@@ -17,6 +17,7 @@ deviceinfo_keyboard="true"
 deviceinfo_external_storage="true"
 deviceinfo_screen_width="1366"
 deviceinfo_screen_height="768"
+deviceinfo_disable_dhcpd="true"
 
 # Bootloader related
 deviceinfo_flash_method="none"
@@ -32,4 +33,5 @@ deviceinfo_cgpt_kpart_size="65536"
 # dtbs from deviceinfo_dtb variable and nothing more, so use "mt8173"
 # board here.
 deviceinfo_depthcharge_board="mt8173"
+deviceinfo_depthcharge_compression="lzma"
 deviceinfo_generate_depthcharge_image="true"

device/community/device-google-peach-pit/APKBUILD

@@ -2,8 +2,8 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-peach-pit
 pkgdesc="Samsung Chromebook 2 (11.6 inch)"
-pkgver=6
-pkgrel=2
+pkgver=7
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="armv7"
@@ -58,7 +58,7 @@ nonfree_firmware() {
 }
 
 sha512sums="
-cbeb0f1fdf4357763eae7ede0b28923ae39c18aa187894baa778bdb20afa728aa97cad63b957d799ffcd1130ae40c3b796e293a2a1c97d9a68bf132ec6ce6d13  deviceinfo
+18e829f0eddcc8a0e64eb5081afa324da060de98478ac17d6199c1cecb4d2e984212c8681e8c75b4552d4dd5bbffff2f60dc8be1884b6ef23daa58319d4274fc  deviceinfo
 e12a68f919182cb4e6812a5dd13fce8dc15266d2ac16aa5f0a31034f111cb403c020ebaaa4d94309f4baf2f71379327c57c08029e27c506d152695e9a2b04b2b  modules-initfs
 e53ca475830930ecfc1fd537702e850e2abcb66fbed521cb6c3a2918d762649254bd0244ec93a47b20dfc593ec3afc9bdebdec1759a7bc96dcbe4800f40893da  90-tap-to-click.conf
 6fe67c8f2e09e3e37297eebaf2a86a32671923a5fd4d18e5aeb10e580fb998e4ddb4a691531a0c8f4b4e70c6f0f7e91008dd836ffca8026d59862c6e829fd996  Peach-Pit-I2S-MAX98090.conf

device/community/device-google-peach-pit/deviceinfo

@@ -17,6 +17,7 @@ deviceinfo_external_storage="true"
 deviceinfo_screen_width="1366"
 deviceinfo_screen_height="768"
 deviceinfo_gpu_accelerated="true"
+deviceinfo_disable_dhcpd="true"
 
 # Bootloader related
 deviceinfo_flash_method="none"

device/community/device-google-snow/APKBUILD

@@ -2,8 +2,8 @@
 # Maintainer: Jenneron <jenneron@protonmail.com>
 pkgname=device-google-snow
 pkgdesc="Samsung Chromebook"
-pkgver=6
-pkgrel=2
+pkgver=7
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="armv7"
@@ -56,7 +56,7 @@ sway() {
 }
 
 sha512sums="
-8f12e32794f68ecc312ef9edde380bffc73f931cf210c8e0a5552f47b325f0f6648a95986ae17ad0a32245308dfd3c1e381377b67e6b96eeae18f97b83621f92  deviceinfo
+475bc214db10d233137e8d9a43bfc4ea0c58e8938e9536fddab6c1d57ed133f37aa3a8ffce196df876af17e7817ccf6894947deaaa624bf3c161298196d866f6  deviceinfo
 e12a68f919182cb4e6812a5dd13fce8dc15266d2ac16aa5f0a31034f111cb403c020ebaaa4d94309f4baf2f71379327c57c08029e27c506d152695e9a2b04b2b  modules-initfs
 8a8f593694528a9323ef4a0aff7e9c6ad45608957eb042d425663f682885c2f95eb01db4fe87b7c43a90de48f3e5f8b10cab4b13c547b5b0d31b924fcb083cad  HiFi.conf
 b163535da7626e3866faa45768c3888f69f90c98d694650e16a7594a03eb91391e166931eb487901217d983bb2dc4e49b99a2a5531740a7d87f8f4f5c3d0cf59  Snow-I2S-MAX98090.conf